CS4922 datasheet(22/34 Pages) CIRRUS

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CS4922

The 8 bit value in the serial shift register is shifted

out by the master. The data is valid on the rising

edge of SCL/SCK and transitions immediately fol-

lowing the falling edge. For SPI, the REQ line will

be de-asserted immediately following the rising

edge of the second to last data bit, of the current

byte being transferred, if there is no data in the

SCPOUT register. The REQ line is guaranteed to

stay de-asserted (high) until the rising edge of the

SCL/SCK for the last data bit. This signals the host

that the transfer is complete.

If there is data placed in SCPOUT prior to the ris-

ing edge of SCL/SCK for the second to last data bit,

then REQ will remain asserted (low). Immediately

following the falling edge of SCL/SCK for the last

data bit, the new data byte will be loaded into the

serial shift register. The host should continue to

read this new byte. It is important to note that once

the data is in the shift register, clocks on the

SCL/SCK line will shift the data bits out of the shift

other bus activity or the data will be lost. If CS is

de-asserted SCK/SCL will not shift the data out.

However the data is still in the shift register. Once

CS becomes active (low) each SCL/SCK will shift

the data out of the register.

If data is placed in SCPOUT after the rising edge of

SCL/SCK for the second to last data bit, but before

the rising edge of SCL/SCK for the last data bit,

REQ will not be asserted until after the rising edge

of SCL/SCK for the last data bit. This should be

treated as a completed transfer. The data written to

SCPOUT will not be loaded into the shift register

on the falling edge of SCL/SCK for the last data bit.

Therefore, a new read operation is required to read

this byte.

4.8 External Flag Pins

The CS4922 has four external flag pins: XF1-XF4.

An external pull-up (2.2 k

Ω typical) is required for

proper operation on each pin. The usage of the XF

pins is completely defined by the application code

running on the CS4922.

The MPEG application, for example, uses XF1 as a

compressed data throttle indicator. When the XF1

pin is low, the host may continue to send com-

pressed data to the CS4922. When XF1 is high, the

SCL/SCK

CDIN

AD6

AD5

AD4

AD3

AD2

AD1

AD0

R/W

CDOUT

REQ

CDOUT

REQ

Figure 17. Control Port Timing, SPI Read

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