CS4922 datasheet(18/34 Pages) CIRRUS

18 / 34 page

CS4922

communication between the on-chip DSP and an

off-chip device such as a micro controller. Figure

13 shows a block diagram of the port.

4.7.1 I

2C Mode

The status of CS sets the mode of the SCP during a

hardware and software reset. If CS is high during a

reset the mode is I2C. Note that in most systems

where I2C is the preferred control mode, CS is con-

nected to the digital supply.

For normal I2C operation SCL/SCK, SDA, and

REQ are used. CS and CDIN are typically connect-

ed to the digital supply. SCL/SCK is the serial

clock input which is always driven by an external

device. SDA is the serial data Input/Output signal.

REQ is the active low request signal, which is driv-

en low when there is valid data in the serial control

port output SCPOUT register.

As an I2C compatible port, data is communicated

on the SDA pin and is clocked by the rising edge of

SCL/SCK. The Philips I2C bus specification pro-

vides details of this interface. Note the CS4922

does not meet the rise time specification of the

SCL/SCK signal. For more details please refer to

the section on Rise Time of SCL/SCK.

Figure 12 shows the relative timing necessary for

an I2C write operation for a single byte. A ‘write’

is defined as the transfer of data from an I2C bus

master to the CS4922 serial control port. A transfer

is initiated with a start condition followed by a 7 bit

address and a read/write bit (set low for a write).

This address is the address assigned to the device

being written to during the transfer. In the case of

the CS4922, this address is stored in the SCPCN

CS4922's Address checking Enable (AEN) bit is

set to zero. The AEN bit must be set high for the

CS4922 to compare the address of the intended I2C

device on the bus to its internal address. This means

the CS4922 will respond to any address on the I2C

bus until its address is initialized and address

checking is enabled. To avoid bus conflicts the

CS4922 should be held in reset (RESET active

low) until the master is ready to communicate with

the CS4922 and sets the address in the SCPCN. The

address can only be set using the I2C bus interface,

so the master should use the intended I2C address

when downloading microcode to the CS4922 to

avoid conflict with other devices on the bus. Once

the microcode is loaded into the CS4922 the micro-

code should either initialize the I2C address or pro-

vide a means for the master to program the I2C

address. If the CS4922 is the only device on the I2C

bus, address checking is optional. However, I2C

bus protocol is still required. In other words, the ad-

dress bits and read/write bit are still required.

If a write to the CS4922 is specified, 8 bits of data

on SDA will be shifted into the input shift register as

shown in Figure 13. When the shift register is full,

the 8 bit data is transferred to the Serial Control

Port Input (SCPIN) register on the falling edge of

the 8th data bit and an acknowledge (ACK) is sent

back to the master..

AUXLR

AUXCLK

AUXOUT

LSB

MSB

20 clks

64 clks

LSB

MSB

LSB

MSB

LSB

MSB

LSB

MSB

LSB

MSB

AUXOUT #1

AUXOUT #3

AUXOUT #5

AUXOUT #2

AUXOUT #4

AUXOUT #6

20 clks

AUXIN #1

AUXIN #3

AUXIN #2

AUXIN #4

20 clks

AUXIN

Figure 11. Multi-channel Auxiliary Data Formats

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