CS4922 datasheet(20/34 Pages) CIRRUS

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CS4922

lowing the falling edge. For I2C the REQ line will

be de-asserted immediately following the rising

edge of the last data bit of the current byte being

transferred, if there is no data in the SCPOUT reg-

ister. The REQ line is guaranteed to stay de-assert-

ed (high) until the rising edge of the SCL/SCK for

the ACK. This signals the host that the transfer is

complete.

If there is data placed in SCPOUT prior to the ris-

ing edge of SCL/SCK for the last data bit, then

REQ will remain asserted (low). Immediately fol-

lowing the falling edge of SCL/SCK for the ACK,

the new data byte will be loaded into the serial shift

byte. It is important to note that once the data is in

the shift register, clocks on the SCL/SCK line will

shift the data bits out of the shift register. A STOP

condition on the bus will not prevent this from oc-

curring. The host must read the byte prior to any

other bus activity or the data will be lost.

If data is placed in SCPOUT after the rising edge of

SCL/SCK for the last data bit, but before the rising

edge of SCL/SCK for the ACK, REQ will not be

asserted until after the rising edge of SCL/SCK for

the ACK. This should be treated as a completed

transfer. The data written to SCPOUT will not be

loaded into the shift register on the falling edge of

SCL/SCK for the ACK. Therefore, a new read op-

eration is required to read this byte.

4.7.2 Rise Time on SCL/SCK

The Philips I2C bus specification allows for rise

times of the SCL/SCK line up to 1

µs. The CS4922

does not meet this specification. If the I2C bus mas-

ter(s) has a rise time in excess of 50 ns the CS4922

will be unable to reliably communicate across the

bus. In some systems a stronger pull-up resistor on

the SCL/SCK line will provide the rise time needed

for proper operation, but this is only helpful when

the current rise time is near 50 ns. In cases where

the CS4922 will be used in a system where a longer

rise time on SCL/SCK is expected, a CMOS com-

patible buffer should be used. Figure 15 shows the

necessary connections. Note the buffer is only used

for the SCL/SCK connecting directly to the

CS4922. Other devices on the I2C bus may need to

hold SCL/SCK low while accepting data.

4.7.3 SPI mode

The status of CS sets the mode of the SCP during a

hardware and software reset. If CS is low during a

reset the mode is SPI. It is important to note that CS

should be low when either a hardware of software

reset is issued to ensure the mode remains SPI.

AD6

AD5

AD4

AD3

AD2

AD1

AD0

R/W

ACK

SDA

SCL/SCK

SDA

SCL/SCK

Start

Stop

REQ

Figure 14. Control Port Timing, I2C® Read

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