CS4922

7

5. This delay is necessary after any rising edge of RESET to allow time for the part to initialize and for

the on-board PLL to stabilize.

Parameter

Symbol

Min

Max

Units

BOOT Setup Time to RESET Rising

350

-

ns

RESET Rising to Boot Hold Time

450

-

ns

CS Setup Time to RESET Rising

(Note 4)

200

-

ns

RESET Rising to CS Hold Time

400

-

ns

RESET Low Time

50

-

µs

SCK/SCL Delay Time from RESET Rising

(Note 5)

2-

ms

SCK/SCL falling to CS rising on last byte of download

3-

µs

BOOT

RESET

SCK/SCL

tbsu tbh

trlow

tcssu

trsc

CS

(SPI)

CS

(I C)

2

tsfcr

Figure 1. Boot Timing