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OPA810

SBOS799A – AUGUST 2019 – REVISED DECEMBER 2019

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Electrical Characteristics: 24 V (continued)

1 kΩ connected to mid-supply

(1).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Test

(4)

Change in input offset from its value when input is biased to midsupply.

(5)

Change in supply voltage from the default test condition with only one of the positive or negative supplies changing corresponding to

+PSRR and -PSRR.

INPUT

Allowable input differential

voltage

see Figure 54

±7

V

C

Common-mode input

impedance

In closed-loop configuration

12 || 2.5

GΩ||pF

C

Differential input capacitance

In open-loop configuration

0.5

pF

C

Most positive input voltage

(4)

V

A

Most negative input voltage

(4)

V

A

Most positive input voltage

for main-JFET stage

See Figure 33

V

C

OUTPUT

Output voltage range high

V

A

B

Output voltage range low

0.23

V

A

0.33

B

Linear output drive (sourcing

and sinking)

48

64

mA

A

Output short-circuit current

108

mA

B

Capacitive load drive

10

pF

C

POWER SUPPLY

Quiescent current per

channel

3.8

4.7

mA

A

PSRR

Power supply rejection ratio

(5)

90

105

dB

A

90

B

AUXILIARY CMOS INPUT STAGE

Gain-bandwidth product

27

MHz

C

Input-referred voltage noise

f = 1 MHz

20

nV/

√Hz

C

Input offset voltage

1.6

mV

A

Input bias current

2

24

pA

A