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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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OPA607 датащи(PDF) 36 Page - Texas Instruments |
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OPA607 датащи(HTML) 36 Page - Texas Instruments |
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36 / 50 page  Place bypass capacitors close to power pins Place output r esi stors close to output pin to minimize para sitic capa citance Gro und and power plan e re mo ved from in ner layers. Gro und fill on outer layers a lso removed Gro und and power plan e e xist on inne r la yer s. Place bypass capacitors close to power pins Remove G ND and Power plan e und er o utp ut and inverting pins to minimize stray PCB capacitance CBYP RF RG + ± VS- CBYP VS+ Representative schematic of a single channe l 1 8 2 7 3 6 4 5 RS CBYP CBYP RS Remove G ND and Power plan e und er o utp ut and inverting pins to minimize stray PCB capacitance Place inpu t resistor close to pin 2 to minimize p arasitic ca pacita nce Place feedback r esistor on the bottom of PCB be tween pin s 2 and 6 RG 36 OPA810 SBOS799A – AUGUST 2019 – REVISED DECEMBER 2019 www.ti.com Product Folder Links: OPA810 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated 11.2 Layout Example Figure 80. Layout Recommendation |
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