PCI6621 datasheet(98/204 Pages) TI

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4−22

Table 4−9. General Control Register Description (Continued)

BIT

SIGNAL

TYPE

FUNCTION

2 ‡

DED_SC_PWR_

CTRL

Dedicated Smart Card power control. This bit determines how power to the dedicated Smart Card

socket is controlled.

0 = Controlled through the SC_PWR_CTRL terminal (default)

1 = Controlled through the VPP voltage of socket B of the CardBus power switch (the design

must ensure that this mode can only be set when CardBus socket B is disabled).

1−0 ‡

ARB_CTRL

Controls top level PCI arbitration:

00 = 1394 OHCI priority

10 = Flash media/SD host priority

01 = CardBus priority

11 = Fair round robin

Note: When flash media/SD host priority is selected, there must be a two-level priority scheme with the

first level being a round robin between the flash media and SD host functions and the second level being

a round robin between the CardBus and 1394 functions.

‡ One or more bits in this register are cleared only by the assertion of GRST.

4.32 General-Purpose Event Status Register

The general-purpose event status register contains status bits that are set when general events occur, and can be

programmed to generate general-purpose event signaling through GPE. See Table 4−10 for a complete description

of the register contents.

Bit

Name

General-purpose event status

Type

RCU

Default

General-purpose event status

Offset:

88h

Type:

Read/Clear/Update, Read-only

Default:

00h

Table 4−10. General-Purpose Event Status Register Description

BIT

SIGNAL

TYPE

FUNCTION

7 ‡

PWR_STS

RCU

Power change status. This bit is set when software changes the VCC or VPP power state of either socket.

6 ‡

VPP12_STS

RCU

12-V VPP request status. This bit is set when software has changed the requested VPP level to or from 12 V

for either socket.

RSVD

Reserved. This bit returns 0 when read. A write has no effect.

4 ‡

GP4_STS

RCU

GPI4 status. This bit is set on a change in status of the MFUNC5 terminal input level if configured as a

general-purpose input, GPI4.

3 ‡

GP3_STS

RCU

GPI3 status. This bit is set on a change in status of the MFUNC4 terminal input level if configured as a

general-purpose input, GPI3.

2 ‡

GP2_STS

RCU

GPI2 status. This bit is set on a change in status of the MFUNC2 terminal input level if configured as a

general-purpose input, GPI2.

1 ‡

GP1_STS

RCU

GPI1 status. This bit is set on a change in status of the MFUNC1 terminal input level if configured as a

general-purpose input, GPI1.

0 ‡

GP0_STS

RCU

GPI0 status. This bit is set on a change in status of the MFUNC0 terminal input level if configured as a

general-purpose input, GPI0.

‡ One or more bits in this register are cleared only by the assertion of GRST.

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