PCI6621 datasheet(65/204 Pages) TI

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3−17

PCI6x21/PCI6x11 internal event, because it depends on the completion of applying power to the socket rather than

on a signal change at the PC Card interface.

3.7.2

Interrupt Masks and Flags

Host software may individually mask (or disable) most of the potential interrupt sources listed in Table 3−10 by setting

the appropriate bits in the PCI6x21/PCI6x11 controller. By individually masking the interrupt sources listed, software

can control those events that cause a PCI6x21/PCI6x11 interrupt. Host software has some control over the system

interrupt the PCI6x21/PCI6x11 controller asserts by programming the appropriate routing registers. The

PCI6x21/PCI6x11 controller allows host software to route PC Card CSC and PC Card functional interrupts to separate

system interrupts. Interrupt routing somewhat specific to the interrupt signaling method used is discussed in more

detail in the following sections.

When an interrupt is signaled by the PCI6x21/PCI6x11 controller, the interrupt service routine must determine which

of the events listed in Table 3−9 caused the interrupt. Internal registers in the PCI6x21/PCI6x11 controller provide

flags that report the source of an interrupt. By reading these status bits, the interrupt service routine can determine

the action to be taken.

Table 3−9 details the registers and bits associated with masking and reporting potential interrupts. All interrupts can

be masked except the functional PC Card interrupts, and an interrupt status flag is available for all types of interrupts.

Notice that there is not a mask bit to stop the PCI6x21/PCI6x11 controller from passing PC Card functional interrupts

through to the appropriate interrupt scheme. These interrupts are not valid until the card is properly powered, and

there must never be a card interrupt that does not require service after proper initialization.

Table 3−9 lists the various methods of clearing the interrupt flag bits. The flag bits in the ExCA registers (16-bit PC

Card-related interrupt flags) can be cleared using two different methods. One method is an explicit write of 1 to the

flag bit to clear and the other is by reading the flag bit register. The selection of flag bit clearing methods is made by

bit 2 (IFCMODE) in the ExCA global control register (ExCA offset 1Eh/5Eh/81Eh, see Section 5.20), and defaults to

the flag-cleared-on-read method.

The CardBus-related interrupt flags can be cleared by an explicit write of 1 to the interrupt flag in the socket event

registers, software must not program the chip through both register sets when a CardBus card is functioning.

3.7.3

Using Parallel IRQ Interrupts

The seven multifunction terminals, MFUNC6−MFUNC0, implemented in the PCI6x21/PCI6x11 controller can be

routed to obtain a subset of the ISA IRQs. The IRQ choices provide ultimate flexibility in PC Card host interruptions.

To use the parallel ISA-type IRQ interrupt signaling, software must program the device control register (PCI offset

92h, see Section 4.39), to select the parallel IRQ signaling scheme. See Section 4.36, Multifunction Routing Status

A system using parallel IRQs requires (at a minimum) one PCI terminal, INTA, to signal CSC events. This requirement

is dictated by certain card and socket-services software. The INTA requirement calls for routing the MFUNC0 terminal

for INTA signaling. The INTRTIE bit is used, in this case, to route socket interrupt events to INTA. This leaves (at a

maximum) six different IRQs to support legacy 16-bit PC Card functions.

As an example, suppose the six IRQs used by legacy PC Card applications are IRQ3, IRQ4, IRQ5, IRQ9, IRQ10,

and IRQ15. The multifunction routing status register must be programmed to a value of 0A9F 5432h. This value

routes the MFUNC0 terminal to INTA signaling and routes the remaining terminals as illustrated in Figure 3−11. Not

shown is that INTA must also be routed to the programmable interrupt controller (PIC), or to some circuitry that

provides parallel PCI interrupts to the host.

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