LP8733 datasheet(36/82 Pages) TI1

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LP8733

SNVSBK2 – SEPTEMBER 2019

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In a similar way, the overload situation is protected during normal operation. If the output voltage falls below 0.35

V and 0.3 V and remains below the threshold level for 1 ms, then the regulator is disabled.

In Buck regulator short-circuit and overload situations, the BUCKx_SC_INT bit in the INT_BUCK register and the

INT_BUCKx bit in the INT_TOP_1 register are set to 1, the BUCKx_STAT bit in BUCK_STAT register is set to 0,

and the nINT signal is pulled low. In LDO regulator short-circuit and overload situations, the LDOx_SC_INT bit in

the INT_LDO register and the INT_LDOx bit in the INT_TOP_1 register are set to 1, the LDOx_STAT bit in the

LDO_STAT register is set to 0, and the nINT signal is pulled low. The host processor clears the interrupt by

writing 1 to the BUCKx_SC_INT or to the LDOx_SC_INT bit. Upon clearing the interrupt, the regulator makes a

new start-up attempt if the regulator is in an enabled state.

7.3.8.3.2

Overvoltage Protection

The LP8733xx device monitors the input voltage from the VANA pin in standby and active operation modes. If

the input voltage rises above the VANAOVP voltage level, the following occurs:

•

All regulators are disabled immediately (without switching ramp or shutdown delays).

•

The pull-down resistors discharge the output voltages, if the pull-down resistors are enabled (the

BUCKx_RDIS_EN = 1 in the BUCKx_CTRL_1 register and the LDOx_RDIS_EN = 1 in the LDOx_CTRL

•

The GPOs are set to logic low level.

•

The nINT signal is pulled low.

•

The OVP_INT bit in the INT_TOP_1 register is set to 1.

•

The BUCKx_STAT bit in the BUCK_STAT register and the LDOx_STAT bit in the LDO_STAT register are set

to 0.

The host processor clears the interrupt by writing 1 to the OVP_INT bit. If the input voltage is above the

overvoltage detection level, then the interrupt is not cleared. The host can read the status of the overvoltage from

the OVP_STAT bit in the TOP_STAT register. The regulators cannot be enabled as long as the input voltage is

above the overvoltage detection level or while the overvoltage interrupt is pending.

7.3.8.3.3

Thermal Shutdown

The LP8733xx has an overtemperature protection function that operates to protect itself from short-term misuse

and overload conditions. When the junction temperature exceeds around 150°C, the regulators are disabled

immediately (without switching ramp and shutdown delays), the TDIE_SD_INT bit in the INT_TOP_1 register is

set to 1, the nINT signal is pulled low, and the device enters STANDBY. The nINT is cleared by writing 1 to the

TDIE_SD_INT bit. If the temperature is above thermal shutdown level, then the interrupt is not cleared. The host

can read the status of the thermal shutdown from the TDIE_SD_STAT bit in the TOP_STAT register. The

regulators cannot be enabled as long as the junction temperature is above the thermal shutdown level or while

the thermal shutdown interrupt is pending.

7.3.8.4 Fault (Power Down)

7.3.8.4.1

Undervoltage Lockout

When the input voltage falls below the VANAUVLO at the VANA pin, the buck and LDO regulators are disabled

immediately (without switching ramp and shutdown delays), the output capacitor is discharged using the

pulldown resistor, and the LP8733xx device enters SHUTDOWN. When the V(VANA) voltage is above the

VANAUVLO threshold level, the device powers up to STANDBY state.

If the reset interrupt is unmasked by default (OTP bit for RESET_REG_MASK is 0 in TOP_MASK_2 register),

then the RESET_REG_INT interrupt bit in the INT_TOP_2 register indicates that the device has been in

SHUTDOWN. The host processor must clear the interrupt by writing 1 to the RESET_REG_INT bit. If the host

processor reads the RESET_REG_INT interrupt bit after detecting an nINT low signal, then it detects that the

input supply voltage has been below the VANAUVLO level (or the host has requested reset with the SW_RESET

bit in the RESET register), and the registers are reset to default values.

7.3.9 Operation of the GPO Signals

The LP8733xx device supports up to two general purpose output signals, GPO and GPO2. The GPO2 signal is

multiplexed with the CLKIN signal. The selection between the CLKIN and GPO2 pin function is set with the

CLKIN_PIN_SEL bit in the CONFIG register.

LP8733 датащи(PDF) 36 Page - Texas Instruments

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