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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LP8733 датащи(PDF) 33 Page - Texas Instruments |
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LP8733 датащи(HTML) 33 Page - Texas Instruments |
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33 / 82 page  V(VANA) VANA_UVLO State Shutdown Read OTP Standby PGOOD pin EN pin VOUT (Buck1) VOUT (LDO0) Buck1 internal powergood LDO0 internal powergood Active Buck1 internal enable LDO0 internal enable 4 ms 2 ms 33 LP8733 www.ti.com SNVSBK2 – SEPTEMBER 2019 Product Folder Links: LP8733 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Figure 19. PGOOD Pin Operation in Continuous Mode 7.3.8.2 Warnings for Diagnosis (Interrupt) 7.3.8.2.1 Output Power Limit The Buck regulators have programmable output peak current limits. The limits are individually programmed for both regulators with the BUCKx_ILIM[2:0] bits in the BUCKx_CTRL_2 register. The current limit settings of master and slave regulators used for the same output voltage rail must be identical. If the load current is increased so that the current limit is triggered, then the regulator continues to regulate at the limit current level (peak current regulation). The voltage may decrease if the load current is higher than the limit current. If the current regulation continues for 20 µs, than the LP8733xx device sets the BUCKx_ILIM_INT bit in the INT_BUCK register and pulls the nINT pin low. The host processor can read the BUCKx_ILIM_STAT bits in the BUCK_STAT register to see if the regulator is still in peak current regulation mode, and the interrupt is cleared by writing 1 to the BUCKx_ILIM_INT bit. The current limit interrupt can be masked by setting the BUCKx_ILIM_MASK bit in the BUCK_MASK register to 1. The Buck overload situation is shown in Figure 20. |
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