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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ADV7330KST датащи(PDF) 16 Page - Analog Devices |
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ADV7330KST датащи(HTML) 16 Page - Analog Devices |
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16 / 76 page  REV. B –16– ADV7330 SR7– SR0 Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting Reset Values 02h Mode Register 0 Reserved 00 Zero must be written to these bits 20h Test Pattern Black Bar 0 Disabled 1 Enabled RGB Matrix 0 Disable Programmable RGB Matrix 1 Enable Programmable RGB Martix Sync on RGB 1 0No Sync 1 Sync on all RGB Outputs RGB/YUV Output 0 RGB component Outputs 1YUV component Outputs SD Sync 0 No Sync Output 1 Output SD Syncs on HSYNC_O/P, VSYNC_O/P, BLANK_O/P HD Sync 0No Sync Output 1 Output HD Syncs on HSYNC_O/P, VSYNC_O/P, BLANK_O/P 03h RGB Matrix 0 xx LSB for GY 03h 04h RGB Matrix 1 x x LSB for RV F0h xx LSB for BU xx LSB for GV xx LSB for GU 05h RGB Matrix 2 x x x x x x x x Bit 9–2 for GY 4Eh 06h RGB Matrix 3 x x x x x x x x Bit 9–2 for GU 0Eh 07h RGB Matrix 4 x x x x x x x x Bit 9–2 for GV 24h 08h RGB Matrix 5 x x x x x x x x Bit 9–2 for BU 92h 09h RGB Matrix 6 x x x x x x x x Bit 9–2 for RV 7Ch 0Ah xx xx xx xx Reserved 0Bh DAC A,B,C Output Level 2 Positive Gain to DAC Output Voltage 0 0 0 0 0 0 0 0 0% 00h 00 00 00 01 0.018% 00 00 00 10 0.036% ……… 00 11 11 11 7.382% 01 00 00 00 7.5% Negative Gain to DAC Output Voltage 1 1 0 0 0 0 0 0 –7.5% 11 00 00 01 –7.382% 10 00 00 10 –7.364% … ……. 11 11 11 11 –0.018% 0Ch Reserved 00h 0Dh Reserved 00h 0Eh Reserved 00h 0Fh Reserved 00h 11h, Bit 2 must also be enabled NOTES 1For more detail, refer to Appendix 7. 2For more detail on the programmable output levels, refer to the Programmable DAC Gain Control section. |
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