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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ADV7330KST датащи(PDF) 65 Page - Analog Devices |
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ADV7330KST датащи(HTML) 65 Page - Analog Devices |
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65 / 76 page  REV. B ADV7330 –65– Mode 2—Master Option (Timing Register 0 TR0 = X X X X X 1 0 1) In this mode, the ADV7330 can generate horizontal and vertical sync signals. A coincident low transition of both HSYNC_O/P and VSYNC_O/P outputs indicates the start of an odd field. A VSYNC_O/P low transition when HSYNC_O/P is high indicates the start of an even field. HSYNC is output on the HSYNC_O/P pin, BLANK on the BLANK_O/P pin, and VSYNC on the VSYNC_O/P pin. PAL = 12 CLOCK/2 NTSC = 16 CLOCK/2 PAL = 132 CLOCK/2 NTSC = 122 CLOCK/2 Cb Y Cr Y PIXEL DATA HSYNC_O/P BLANK_O/P VSYNC_O/P Figure 78. SD Timing Mode 2—Even to Odd Field Transition Master/Slave PAL = 864 CLOCK/2 NTSC = 858 CLOCK/2 PAL = 132 CLOCK/2 NTSC = 122 CLOCK/2 PIXEL DATA PAL = 12 CLOCK/2 NTSC = 16 CLOCK/2 Cb Y Cr Y Cb HSYNC_O/P BLANK_O/P VSYNC_O/P Figure 79. SD Timing Mode 2—Odd to Even Field Transition Master/Slave |
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