ADV7330KST datasheet(6/76 Pages) AD

6 / 76 page

REV. B

–6–

ADV7330

TIMING SPECIFICATIONS

(VAA = 2.375 V to 2.625 V, VDD = 2.375 V to 2.625 V; VDD_IO = 2.375 V to 3.6 V, VREF = 1.235 V,

RSET = 3040

, RLOAD = 300

. All specifications TMIN to TMAX (0 C to 70 C), unless otherwise noted.)

Parameter

Min

Typ

Max

Unit

Conditions

MPU PORT

SCLOCK Frequency

400

kHz

SCLOCK High Pulsewidth, t1

0.6

µs

SCLOCK Low Pulsewidth, t2

1.3

µs

Hold Time (Start Condition), t3

0.6

µs

After this period, the first clock is generated

Setup Time (Start Condition), t4

0.6

µsRelevant for repeated start condition

Data Setup Time, t5

100

SDATA, SCLOCK Rise Time, t6

300

SDATA, SCLOCK Fall Time, t7

300

Setup Time (Stop Condition), t8

0.6

µs

RESET Low Time

100

ANALOG OUTPUTS

Analog Output Delay

7ns

Output Skew

CLOCK CONTROL AND PIXEL PORT

fCLK

MHz

Progressive scan mode

fCLK

MHz

HDTV mode/async mode

Clock High Time, t9

% of one clk cycle

Clock Low Time, t10

% of one clk cycle

Data Setup Time, t11

2.0

Data Hold Time, t12

2.0

SD Output Access Time, t13

SD Output Hold Time, t14

5.0

HD Output Access Time, t13

HD Output Hold Time, t14

5.0

PIPELINE DELAY

clk cycles

SD (2

×, 16×)

clk cycles

SD component mode (16

×)

clk cycles

PS (1

×)

clk cycles

PS (8

×)

clk cycles

HD (2

×, 1×)

NOTES

1Guaranteed by characterization.

2Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of the DAC output full-scale transition.

3Data: C [9:0]; Y [9:0], S[9:0].

Control:

HSYNC_I/P, VSYNC_I/P, BLANK_I/P, HSYNC_O/P, VSYNC_O/P, BLANK_O/P.

4SD, PS = 27 MHz, HD = 74.25 MHz.

Specifications subject to change without notice.

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