ADV7330KST datasheet(13/76 Pages) AD

13 / 76 page

REV. B

ADV7330

–13–

MPU PORT DESCRIPTION

The ADV7330 supports a 2-wire serial (I

2C compatible) micro-

processor bus driving multiple peripherals. This bus operates

in an Open Drain configuration. Two inputs, serial data

(SDA) and serial clock (SCL), carry information between any

devices connected to the bus. Each slave device is recognized by a

unique address. The ADV7330 has four possible slave ad-

dresses for both read and write operations. These are unique

addresses for each device and are illustrated in Figure 12. The

LSB sets either a read or write operation. Logic 1 corresponds to

a read operation, while Logic 0 corresponds to a write operation.

A1 is set by setting the ALSB pin of the ADV7330 to Logic 0

or Logic 1. When ALSB is set to 1, there is greater input band-

width on the I

2C lines, which allows high speed data transfers

on this bus. When ALSB is set to 0, there is reduced input

bandwidth on the I

2C lines, which means that pulses of less

than 50 ns will not pass into the I

2C internal controller. This

mode is recommended for noisy systems.

ADDRESS

CONTROL

SET UP BY

ALSB

READ/WRITE

CONTROL

WRITE

READ

Figure 12. ADV7330 Slave Address = D4h

To control the various devices on the bus, the following proto-

col must be followed. First the master initiates a data transfer by

establishing a start condition, defined by a high-to-low transition

on SDA, while SCL remains high. This indicates that an address/

data stream will follow. All peripherals respond to the start

condition and shift the next eight bits (7-bit address + R/

W bit).

The bits are transferred from MSB down to LSB. The periph-

eral that recognizes the transmitted address responds by pulling

the data line low during the ninth clock pulse. This is known as

an acknowledge bit. All other devices withdraw from the bus at

this point and maintain an idle condition. The idle condition is

when the device monitors the SDA and SCL lines waiting for the

start condition and the correct transmitted address. The R/

bit determines the direction of the data.

A Logic 0 on the LSB of the first byte means that the master

will write information to the peripheral. A Logic 1 on the LSB

of the first byte means that the master will read information

from the peripheral.

The ADV7330 acts as a standard slave device on the bus. The

data on the SDA pin is eight bits long, supporting the 7-bit

addresses plus the R/

W bit. It interprets the first byte as the device

address and the second byte as the starting subaddress. There

is a subaddress auto-increment facility. This allows data to be

written to or read from registers in ascending subaddress

sequence, starting at any valid subaddress. A data transfer is

always terminated by a stop condition. The user can also access

any unique subaddress register on a one-by-one basis without

having to update all the registers.

PIN FUNCTION DESCRIPTIONS (continued)

Pin Number

Mnemonic

I/O

Function

10, 56

VDD

PDigital Power Supply.

VAA

PAnalog Power Supply.

45, 47

TEST15, TEST16

Not used, do not connect.

EXT_LF

External Loop Filter for the Internal PLL.

RTC_SCR_TR

Multifunctional Input: Real-Time Control (RTC) Input, Timing Reset Input,

Subcarrier Reset Input.

BLANK_O/P

Video Blanking Control Signal. For HD and PS, this input is active high. For SD input,

this output is active low.

HSYNC_O/P

OVideo Horizontal Sync Control Signal.

VSYNC_O/P

OVideo Vertical Sync Control Signal.

2CI

This input pin must be tied high (VDD_IO) for the ADV7330 to interface over the I

2C port.

GND_IO

Digital Input/Output Ground.

42–44

No Connect.

VREF

I/O

Optional External Voltage Reference Input for DACs or Voltage Reference Output

(1.235 V).

TERMINOLOGY

Standard definition video, conforming to ITU-R

BT.601/656.

High definition video, such as progressive scan or HDTV.

Progressive scan video, conforming to SMPTE 293M,

ITU-R BT.1358, BTA T-1004EDTC2, BTA1362

HDTV

High definition television video, conforming to SMPTE

274M or SMPTE 296M.

YCrCb

SD, PS, or HD component digital video.

YPrPb

SD, PS, or HD component analog video.

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