ADP1071-2ARWZ-R7 datasheet(17/27 Pages) AD

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Data Sheet

ADP1071-1/ADP1071-2

Rev. B | Page 17 of 27

SOFT START PROCEDURE

The following procedure assumes that the VDD2 pin is

powered directly from the output voltage of the power supply.

To ensure a smooth output voltage ramp during startup, the soft

start sequence is controlled by two soft start control circuits,

one in the primary (for open-loop soft start using the GATE

pin) and the other in the secondary (for closed-loop soft start,

using the SS2 pin). Proper handshaking between the primary side

and the secondary side is needed prior to the secondary side

taking control.

The open-loop soft start time is determined by the resistor on

the GATE pin prior to startup. The primary peak current is

increased gradually every switching period. The slew rate of the

increase in peak current is determined by selecting the GATE

resistor prior to startup. The current increases from a minimum

of 0 A to a maximum of 120 mV/RSENSE. This rate is the open-

loop soft start. Four speeds are available: 4 × 775, 16 × 775,

64 × 775, and 256 × 775 switching periods for resistors 100 kΩ,

10 kΩ, 22 kΩ, and 47 kΩ, respectively.

During this time, the ADP1071-1/ADP1071-2 start firing the

PWM pulses and the output voltage continues to build up

slowly if the average current on the secondary side exceeds the

load current. Because the ADP1071-1/ADP1071-2 are current

mode controllers, the output capacitor starts charging only

when the primary current limit exceeds the load current

requirement.

The handshaking process is as follows.

When VDD2 reaches the UVLO of approximately 3.5 V, the

internal circuitry on the secondary side is activated and the

ADP1071-1/ADP1071-2 initiate the following two processes:

1. The ADP1071-1/ADP1071-2 make the voltage on the

SS2 pin equal to the value on the FB pin, with an SS2 pin

current, at 10 times the nominal current source of 20 µA

on the SS2 pin.

2. Simultaneously, the current limit on the primary side is

transferred over to the secondary side and the voltage on

the COMP pin is made equal to the instantaneous current

limit of ±100 mV. There is a timeout for this process, which

is 1.5 ms after the VDD2 UVLO threshold is crossed.

When this process is satisfied, the transmission of the COMP signal

occurs from the secondary to the primary side. The ADP1071-1/

ADP1071-2 transmit the COMP signal by continuously sampling

the analog signal at the COMP pin. The sampled value is then

transmitted using a proprietary scheme to the primary side

where the instantaneous value of the CS pin is compared to the

COMP level to determine the falling edge of the GATE pulse.

The COMP signal is, therefore, a representation of the primary

current limit.

After COMP transmission begins, the primary side receives the

signal and control is completely handed over to the secondary

side when either the received level of COMP on the primary

side is within ±100 mV or up to 128 switching periods

(typically 8) have passed, starting from the first pulse being

transmitted to the primary side.

Then, after the control is handed over to the secondary side, the

closed-loop soft start begins, where the SS2 capacitor is charged

at a nominal rate of 20 µA. The output voltage then rises to the

regulation voltage based on the SS2 pin voltage. The voltage on

the SS2 pin continues to rise to 1.2 V, that is, the steady state

voltage on the FB pin. At this stage, the power supply is in

regulation, and the output voltage is at its target value.

At the end of the soft start process, the voltage on the SS2 pin

continues to rise to approximately 1.4 V. In steady state, the

FB pin (that is, the reference voltage) is 1.2 V.

The SR1 and SR2 synchronous drivers begin to pulse after

VDD2 crosses the UVLO threshold.

If the voltage at the VDD2 pin is greater than the UVLO voltage,

such as a soft start from the precharged output, or if the VDD2 pin

is powered by an external supply, the secondary side assumes

control from the moment the EN pin is enabled, and only SS2 is

used for the soft start procedure.

When initiating a soft start from the precharged output, the

SS2 pin tracks the FB pin and then initiates a soft start. This

process eliminates any glitches in the output voltage.

When soft starting into a precharged output, the SR gate is

prevented from turning on until the SS2 voltage reaches the

precharged voltage at the FB pin. This soft start scheme prevents

the output from being discharged, and it prevents reverse current.

Under abnormal situations, such as a shorted load or a transient

condition on the load during the soft start process, FB may not

be able to track SS2 accurately. If this condition occurs before the

VDD2 UVLO threshold is crossed, the open loop soft start is in

effect. If it occurs after the VDD2 UVLO threshold is crossed,

SS2 tracks the FB pin and then continues with the soft start

process until the regulation voltage is reached. In all conditions,

control is handed over to the secondary side if FB ≥ 1.2 V.

When the secondary VDD2 is directly powered by the output of

the converter, the minimum output voltage required is higher

than the secondary UVLO voltage. For output voltages less than

the secondary UVLO voltage, a third winding is needed to generate

an auxiliary voltage to power the secondary side circuitry. Alter-

nately, in most cases, a diode resistor capacitor combination from

the switch node can provide the voltage to VDD2.

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