ADP1071-2ARWZ-R7 datasheet(24/27 Pages) AD

24 / 27 page

ADP1071-1/ADP1071-2

Data Sheet

Rev. B | Page 24 of 27

any voltage waveform varying between 0 V and some limiting

value. The limiting value can be positive or negative, but the

voltage cannot cross 0 V.

RATED PEAK VOLTAGE

Figure 26. Bipolar AC Waveform

RATED PEAK VOLTAGE

Figure 27. Unipolar AC Waveform

RATED PEAK VOLTAGE

Figure 28. DC Waveform

LAYOUT GUIDELINES

The layout guidelines for the primary side are as follows:

Ground all the capacitors to their respective grounds. For

example, ground the VREG1 capacitor to AGND1.

Use the CS pin and the AGND1 pin to differentially sense

the primary current measurement through the sense

resistor. Do not cross the CS and AGND1 traces for current

sensing across any switch nodes.

Place a capacitor (33 pF to 470 pF typical) close to the

CS pin, connected to AGND1.

Place resistors (1 Ω to 5 Ω typical) in series with GATE and

the main power MOSFET. These resistors aid in eliminating

any ringing on the drive voltages. Use a 100 nF capacitor

on the MODE pin if LLM is used in noisy environments.

Ensure that RT pin resistor is Kelvin connected to AGND1

and not to a ground plane to avoid noise pickup.

The layout guidelines for the secondary side are as follows:

Ground all the capacitors to their respective grounds. For

example, ground the SS2 capacitor to AGND2.

Place resistors (1 Ω to 5 Ω) in series with SRx and the

synchronous MOSFET. These resistors aid in eliminating

any ringing on the drive voltages.

The ground plane on the secondary side must be

connected to AGND2. The negative terminal of the output

voltage must be Kelvin connected to the AGND2 pin.

Use the FB pin and the AGND2 pin to remotely differentially

sense the output voltage by connecting AGND2 to the

negative terminal of the output voltage using a 0 Ω resistor.

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