ADA4945-1ACPZ-R2 datasheet(40/44 Pages) AD

40 / 44 page

ADA4945-1

Data Sheet

Rev. 0 | Page 40 of 44

INPUT COMMON-MODE VOLTAGE RANGE

The input common-mode range at the summing nodes of the

ADA4945-1 is specified as −VS to +VS − 1.3 V. By extending the

input common-mode range down to −VS, the ADA4945-1 is

especially well suited to dc-coupled, single-ended-to-differential,

and single-supply applications, such as ADC driving.

INPUT AND OUTPUT CAPACITIVE AC COUPLING

Although the ADA4945-1 is best suited to dc-coupled applications,

it is possible to use the device in ac-coupled circuits. Input ac

coupling capacitors can be inserted between the source and RG.

This ac coupling blocks the flow of the dc common-mode

feedback current and causes the ADA4945-1 dc input common-

mode voltage to equal the dc output common-mode voltage.

These ac coupling capacitors must be placed in both loops to keep

the feedback factors matched. Output ac coupling capacitors can

be placed in series between each output and the respective load

of each output.

SETTING THE OUTPUT COMMON-MODE VOLTAGE

The VOCM pin of the ADA4945-1 is internally biased at a voltage

approximately equal to the midway between the output voltage

clamps, ((+VCLAMP) + (−VCLAMP))/2. Relying on this internal bias

results in an output common-mode voltage that is within

approximately 100 mV of the expected value.

When more accurate control of the output common-mode level is

required, it is recommended that an external source, or resistor

divider (10 kΩ or greater resistors), be used. The output

common-mode offset listed in Table 2, Table 5, and Table 8

assumes that the VOCM input is driven by a low impedance voltage

source.

It is also possible to connect the VOCM input to a common-mode

level (CML) output of an ADC. However, care must be taken to

ensure that the output has sufficient drive capability. The input

impedance of the VOCM pin is approximately 125 kΩ.

DISABLE PIN

The ADA4945-1 features a DISABLE pin that can be used to

minimize the quiescent current consumed when the device is

not being used. DISABLE is asserted by applying a low logic level

to the DISABLE pin. The logic level for the DISABLE pin is

referenced to DGND. See Table 3, Table 6, and Table 9 for the

threshold limits.

The DISABLE pin features an internal pull-up network that

enables the amplifier for normal operation. The ADA4945-1

DISABLE pin can be left floating (that is, no external

connection is required) and does not require an external pull-

up resistor to ensure normal on operation (see Figure 110).

When the ADA4945-1 is disabled, the output is high impedance.

Note that the outputs are tied to the inputs through the feedback

resistors and to the source using the gain resistors. In addition,

there are back to back diodes on the input pins that limit the

differential voltage to 1.2 V.

DISABLE

AMPLIFIER

BIAS CURRENT

–VS

+VS

DGND

Figure 110. DISABLE Pin Circuit

DRIVING A CAPACITIVE LOAD

A purely capacitive load reacts with the bond wire and pin

inductance of the ADA4945-1, resulting in high frequency

ringing in the transient response and loss of phase margin. One

way to minimize this effect is to place a resistor in series with

each output to buffer the load capacitance. The resistor and load

capacitance form a first-order, low-pass filter. Therefore, the

resistor value must be as small as possible. In some cases, the

ADCs require small series resistors to be added on their inputs.

Figure 111 shows the capacitive load vs. the series resistance

required to maintain a minimum 45° of phase margin. The test

circuit is shown in Figure 112.

100

1000

LOAD CAPACITANCE (pF)

FULL POWER MODE

LOW POWER MODE

Figure 111. Series Resistance vs. Load Capacitance

+IN

–OUT

+OUT

–FB

+FB

–IN

VOCM

0.1µF

+5V

–5V

VIN

Figure 112. Series Resistance with a Capacitive Load Test Circuit

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