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ADA4945-1ACPZ-R2 датащи(PDF) 36 Page - Analog Devices

номер детали ADA4945-1ACPZ-R2
подробное описание детали  High Speed Offset Drift Fully Differential ADC Driver
PDF  44 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

ADA4945-1ACPZ-R2 датащи(HTML) 36 Page - Analog Devices

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ADA4945-1
Data Sheet
Rev. 0 | Page 36 of 44
OUTPUT VOLTAGE CLAMP
In addition to the differential and common-mode signal paths,
the ADA4945-1 implements clamping circuits to protect the
input devices of circuits being driven by the ADA4945-1,
hereafter assumed to be an ADC, from being overdriven and
potentially damaged. These clamping circuits use both
differential and common-mode feedback to limit the output
voltages to a range defined by the voltage applied to two
reference pins, +VCLAMP and −VCLAMP. These high impedance
pins are typically connected to potentials that define the
allowable input range of the ADC, which are the ADC reference
voltages (+VREF and −VREF) for most ADCs.
As shown in Figure 100, the common-mode clamping circuit
senses the output voltage midpoint and applies a common-
mode feedback signal to prevent VOUT, cm from exceeding
+VCLAMP or going below −VCLAMP.
–OUT
+VCLAMP
UPPER
COMMON-MODE
CLAMP
LOWER
COMMON-MODE
CLAMP
iCLAMP (CM)
–VCLAMP
+OUT
Figure 100. Common-Mode Clamp Block Diagram
The differential clamping circuit, shown in Figure 101, senses
each output (+OUT and −OUT) and applies a differential
feedback signal to prevent either output from exceeding
(+VCLAMP + 0.5 V) or going below (−VCLAMP − 0.5 V). The
approximately 500 mV offset voltage is designed to allow the
outputs to fully use the input range of the ADC without any
clamp engagement, while providing input protection prior to
the turn on of the ADC input protection diodes. This feature
allows the ADA4945-1 to provide a full-scale signal to the ADC
without incurring any clamp induced distortion, thus
maximizing signal-to-noise ratio (SNR) and linearity while
protecting the ADC inputs.
–OUT
+VCLAMP
UPPER
DIFFERENTIAL
CLAMP
iCLAMP (DIFF)
+OUT
+
500 mV
LOWER
DIFFERENTIAL
CLAMP
–VCLAMP
500 mV
iCLAMP (DIFF)
Figure 101. Differential Clamp Block Diagram
By applying a differential feedback signal in response to one or
both outputs exceeding the clamp reference voltages, both
outputs are limited equally, even if only one output exceeds one
of the clamp reference voltages. This feature allows the ADA4945-
1 to maintain a constant output common-mode voltage even
while clamping the differential outputs, which enables a faster
system recovery from a clamped condition.
In systems where output clamping is not desired, the upper
output clamp can be disabled by connecting +VCLAMP to +VS,
and the lower output clamp can be disabled by connecting
−VCLAMP to −VS. If one clamp is disabled (for example, −VS =
−VCLAMP = 0 V), the other can be remain active, and the output
is limited when either or both outputs reaches the active clamp
reference.
An additional feature of the ADA4945-1 is the use of a resistor
divider between the +VCLAMP and −VCLAMP pins, as shown in
Figure 99, to set the default potential on the VOCM pin when the
pin is not externally driven. Because the +VCLAMP and −VCLAMP
pins are typically set to the maximum and minimum desired
input voltage of the ADC (for example, +VREF and −VREF),
respectively, this resistor divider sets the output common-mode
voltage of the ADA4945-1 at the midpoint of the ADC input
range by default. By contrast, most fully-differential amplifiers
use a resistor divider between the amplifier supply voltages to
set the default output common-mode voltage, which may not be
optimal for maximizing ADC input range usage.
POWER MODES
The ADA4945-1 implements two fully characterized active
power modes (full power, low power) and a disable mode to
optimize system power and performance trade-offs. The
transition time from disable mode to either of the active power
modes is fast (<2 μs), allowing additional power savings by
dynamically placing the ADA4945-1 in disable mode when the
output voltage is not needed (for example, between ADC
samples in low data rate systems).



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