GD9FS1G8F2ALG datasheet(18/55 Pages) GIGADEVICE

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GD9Fx1GxF2A

8. OPERATION DESCRIPTION

8.1 Page Read Operation

8.1.1 Common Page Read (00H-30H)

Read is initiated by writing 00H-30H to the command register along with four address cycles. After initial power up, 00h

command is latched, and the first page of the first block has been read to cache, ready for random read out. Therefore only

4 address cycles and 30H command initiates that operation after initial power up. The 2176 bytes of data within the selected

page are transferred to the data registers. The system controller can detect the completion of this data transfer (tR) by

analyzing the output of R/B# pin. Once the data in a page is loaded into the data registers, they may be read out in tRC by

sequentially pulsing RE#. The repetitive high to low transitions of the RE# clock make the device output the data starting

from the selected column address up to the last column address.

After the last data has been read out, CE# may be pulled up for some time to end the read operation, while during the RE#

toggle cycle, CE# may be don't care when RE# is high

. The CE# Don’t Care feature may simplify the system interface,

which allows controller to directly download the code from flash device, and the CE# transitions will not stop the read

operation during the latency time.

00h

Col. Add1

Col. Add2

Row Add1

Row Add2

30h

DOUT

N+1

tCLS

tCLH

tCS

tCH

tCLR

tCLS

tCLH

tCS

tCH

tRC

tWB

tWC

tALS

tCHZ

tCEA

tRR

tREA

Data out from

Col.Add.N

CLE

CE#

WE#

RE#

I/Ox

RY/BY#

ALE

tDS tDH

Col.Add .N

Figure 14: Common Page Read figures

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