GD5F1GQ4REFJS datasheet(45/60 Pages) GIGADEVICE

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SPI(x1/x2/x4) NAND Flash

13.5 Internal ECC

The serial device offers data corruption protection by offering optional internal ECC. READs and PROGRAMs with internal

ECC can be enabled or disabled by setting feature bit ECC_EN. ECC is enabled after device power up, so the default

READ

and PROGRAM commands operate with internal ECC in the “active” state. To enable/disable ECC, perform the

following command sequence:

• Issue the SET FEATURES command (1FH).

• Set the feature bit ECC_EN as you want:

To enable ECC, Set ECC_EN to 1.

To disable ECC, Clear ECC_EN to 0.

During a PROGRAM operation, the device calculates an ECC code on the 2k page in the cache register, before the page

is written to the NAND Flash array.

During a READ operation, the page data is read from the array to the cache register, where the ECC code is calculated

and compared with the ECC code value read from the array. If error bits are detected, the error is corrected in the cache

register. Only corrected data is output on the I/O bus. The ECC status bit indicates whether or not the error correction was

successful. The ECC Protection table below shows the ECC protection scheme used throughout a page.

With internal ECC, the user must accommodate the following:

• Spare area definitions provided in the ECC Protection table below. User meta data I is not protected by internal ECC

and User meta data II is protected by internal ECC.

• ECC can protect main data and spare areas data. Any data wrote to the ECC area are ignored.

Table13-7. ECC Protection and Spare Area

Min Byte Address

Max Byte Address

ECC Protected

Area

Description

000H

1FFH

Yes

Main 0

User data 0

200H

3FFH

Yes

Main 1

User data 1

400H

5FFH

Yes

Main 2

User data 2

600H

7FFH

Yes

Main 3

User data 3

800H

803H

No(2)

Spare 0

User meta 0 data I(1)

804H

80FH

Yes

Spare 0

User meta 0 data II

810H

813H

No(2)

Spare 1

User meta 1 data I

814H

81FH

Yes

Spare 1

User meta 1 data II

820H

823H

No(2)

Spare 2

User meta 2 data I

824H

82FH

Yes

Spare 2

User meta 2 data II

830H

833H

No(2)

Spare 3

User meta 3 data I

834H

83FH

Yes

Spare 3

User meta 3 data II

840H

87FH

Yes

Spare area

Internal ECC parity data

Note:

1. 800H is reserved for initial bad block mark

2. There is no internal ECC for this area, so external protection must be provided by the user. Please see

AN-00180-GD5FxGxxxExxx for detailed information

When Internal ECC is enabled，user cannot program the Address 840H~87FH but user can read the Address

840H~87FH.

When Internal ECC is disabled, the whole page area is open for user.

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