GS3470 datasheet(24/169 Pages) SEMTECH

24 / 169 page

GS3470

Final Data Sheet

Rev.8

PDS-060500

September 2017

24 of 169

Semtech

www.semtech.com

4.2.2 Device Reset

Note: On power-up, the device must be reset to operate correctly.

In order to initialize all internal operating conditions to their default states, hold the

RESET signal LOW for a minimum of treset = 1ms after all power supplies are stable. There

are no requirements for power supply sequencing.

When held in reset, all device outputs are driven to a high-impedance state, with the

exception of SDOUT. SDOUT continues normal operation during reset.

GSPI access is restored 10 clock cycles after RESET is de-asserted.

All output buffers (including the PCLK output), are set to high-impedance in Reset mode

(RESET = LOW).

Figure 4-3: Reset Pulse

4.3 Modes of Operation

4.3.1 Auto and Manual Mode

The lock detection algorithm is a continuous process, beginning at device power-up or

after a system reset. It continues until the device is powered down or held in reset.

The device first determines if a valid serial digital input signal has been presented to the

device. If no valid serial data stream has been detected, the serial data into the device is

considered invalid, and the LOCKED signal is LOW.

Once a valid input signal has been detected, the device attempts to detect the presence

of either TRS words or DVB-ASI sync words.

By default, the device powers up in Auto mode (the AUTO_MAN bit in the host interface

is set HIGH). In this mode, the device operating frequency toggles between 3G, HD, and

SD rates as it attempts to lock to the incoming data rate. As it searches through rates,

PCLK output cycles through 148.5MHz, 74.25MHz, 27MHz, and 13.5MHz. The PCLK

output pin can be set to be high-impedance when not locked through GSPI.

When the device is operating in Manual mode (AUTO_MAN bit in the host interface

bits in the host interface. RATE_SEL_TOP[0] = SD/HD and RATE_SEL_TOP[1] = 3G/HD.

Note: The SD/HD bit takes precedence over the 3G/HD bit, so if the SD/HD bit is HIGH,

the 3G/HD bit is ignored.

Supply Voltage

RESET

treset

95% of Nominal Level

Nominal Level

Reset

treset

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