IP175G datasheet(42/69 Pages) ETC2

42 / 69 page

IP175G/GI/GH/GHI

Data Sheet

42 / 69

November 27, 2012

IP175Gx-DS-R01.3

6.5

Table 11 Register Page mode Control Register table

MII register 20 of PHY0~4 (Each PHY has its own MII register 20 with different PHY address)

PHY

MII

R/W

Description

Default

Page Control Register

20[4:0]

Reg16~31_Page_Sel[4:0]

00000

The other Registers are reserved registers. User is inhibited to access to these registers. It may

introduce abnormal function to write these registers.

6.6

WOL+ Control Register

Table 12 WOL+ Control Register table

page

MII

R/W

Description

Default

PHY WOL+ Control Register

16.[15]

WOL+ Interrupt Enable

Set high to enable WOL+ interrupt

1=Enable

0=Disable

16.[14]

WOL+ Level Trigger

This bit is used to select the output mode of WOL+ interrupt.

1=Level trigger (Low goes high or high goes low when WOL+

interrupt)

0=Edge trigger (Positive pulse or negative pulse when WOL+

interrupt)

16.[13]

WOL+ Positive Trigger

This bit is used to select the polarity of WOL+ interrupt.

1=Low goes high or positive pulse

0=High goes low or negative pulse

16.[12]

Sense Link Change

Set high to enable WOL+ interrupt when link change is sensing.

1=Enable

0=Disable

16.[11]

Sense Magic Packet

Set high to enable WOL+ interrupt when magic packet is

receiving.

1=Enable

0=Disable

16.[10]

Sense Any Packet

Set high to enable WOL+ interrupt when any packet is receiving.

1=Enable

0=Disable

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