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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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IP175G датащи(PDF) 25 Page - List of Unclassifed Manufacturers |
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IP175G датащи(HTML) 25 Page - List of Unclassifed Manufacturers |
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25 / 69 page  IP175G/GI/GH/GHI Data Sheet 25 / 69 November 27, 2012 Copyright © 2012, IC Plus Corp. IP175Gx-DS-R01.3 4.11 Buffer Aging When buffer aging was enabled, a frame stayed in output port for transmission is discarded if buffer aging time has exceeded one second. The buffer aging time is the maximum delay time for transmission on output port. This function can be set from MII register 20.13.13. 4.12 LED display (normal operation) Normal operation LED_O_SEL[1:0] LINK_LED SPEED_LED FDX_LED 00 Off: 100 Mbps link fail On: 100 Mbps link ok Flash: TX/RX Off: no collision Flash: collision Off: 10 Mbps link fail On: 10 Mbps link ok Flash: TXRX 01 Off: link fail On: link ok Off: 10 Mbps On: 100 Mbps Off: half duplex On: full duplex Flash: collision 10 Off: 100 Mbps link fail On: 100 Mbps link ok Flash: TX/RX Off: half duplex On: full duplex Flash: collision Off: 10 Mbps link fail On: 10 Mbps link ok Flash: TXRX 11 Off: link fail On: link ok Flash: TX/RX Off: 10 Mbps On: 100 Mbps Off: half duplex On: full duplex Flash: collision Flash behavior: Off 105ms On 105ms Off 105ms … 4.13 Serial LED Mode IP175G/GH supports serial LED mode and can be setting MII register SERIAL_LED_EN to 1 by MII page3 register 16[12]. There are no enough pins for LED and IP175G/GH sends out LED information through pin 47 (SCLK) and pin 48 (SDATA). It is necessary to use TTL chip to decode and drive LED. The application circuit is shown below. IP175G/GH supports two types of serial LED mode and can be setting by MII page3 register 16[11]. The default value is 0 (SERIAL_LED_MODE = 0) and can be setting to 1 by MII page3 register 16[11]. 4.13.1 Supports link LED only IP175G/GH supports link LED only when setting SERIAL_LED_MODE to 1 and SERIAL_LED_EN to 1. Figure 13 Serial LED Link/Activity Mode 74HC164 PVDD QA QB QC QD QE QF QG QH A CLK CLR B PVDD RESET SCLK SDATA PORT 4 LINK/ACT LED PORT 3 LINK/ACT LED PORT 2 LINK/ACT LED PORT 1 LINK/ACT LED PORT 0 LINK/ACT LED |
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