PRELIMINARY TECHNICAL DATA

REV. PrF 09/2003

–28–

AD5380

AD538X

CONTROLLER/

DSP PROCESSOR*

ADDRESS

DECODE

D15

D0

DATA

BUS

UPPER BITS OF

ADDRESS BUS

A2

A1

A0

R/W

*ADDITIONAL PINS OMITTED FOR CLARITY

D13

D0

CS

LDAC

A2

A1

A0

WR

A3

A4

A5

REG1

REG0

A3

A4

A5

AD5380 PARALLEL INTERFACE

The SER/

PAR pin must be tied low to enable the parallel interface and disable the serial interfaces. Figure 5 shows the

timing diagram for a parallel write. The parallel interface is controlled by the following pins:

CS

CS

CS

CS

CS Pin

Active low device select pin.

WR

WR

WR

WR

WR Pin

On the rising edge of

WR , with CS low, the address on pins A5-A0 are latched and data present on the data bus is

loaded into the selected input registers.

REG0, REG1 Pins

The REG0 and REG1 pins determine the destination register of the data being written to the AD5380. See Table I.

A5-A0 Pins

Each of the 40 DAC channels can be addressed individually.

DB13-DB0 Pins

The AD5380 accepts a straight 14-bit parallel word on DB13-DB0 where DB13 is the MSB and DB0 is the LSB.

MICROPROCESSOR INTERFACING

Parallel Interface

Figure 14 . AD5380 -Parallel Interface