PRELIMINARY TECHNICAL DATA

REV. PrF 09/2003

–22–

AD5380

HARDWARE FUNCTIONS

Reset Function

Bringing the

RESET line low resets the contents of all internal registers to their power-on-reset state. Reset is a negative

edge sensitive input. The default corresponds to m at fullscale and c at zero. The contents of the DAC registers are

cleared setting VOUT0-VOUT39 to zero volts. This sequence takes 300us (typ). The falling edge of

RESET initiates

the reset process and

BUSY goes low for the duration returning high when RESET is complete. While BUSY is low

all interfaces are disabled and all LDAC pulses are ignored. When BUSY returns high the part resumes normal

operation and the status of the

RESET pin is ignored till the next falling edge is detected.

Asynchronous Clear Function

Bringing the

CLR line low clears the contents of the DAC registers to the data contained in the user configurable CLR

register and sets VOUT0-VOUT39 accordingly. This function can be used in system calibration to load zeroscale and

fullscale to all channels together.The execution time for a CLR is 32us.

BUSY

BUSY

BUSY

BUSY

BUSY and

LDAC

LDAC

LDAC

LDAC

LDAC Functions

BUSY is a digital cmos output indicating the status of the AD5380 device. The value of x2 (x2 is the internal data

loaded to the DAC data register) is calculated each time the user writes new data to the corresponding x1, c or m regis-

ters. During the calculation of x2 the

BUSY output goes low. While BUSY is low the user can continue writing new data

to the x1, m or c registers but no DAC output updates can take place. The DAC outputs are updated by taking the

LDAC input low. If LDAC goes low while BUSY is active, the LDAC event is stored and the DAC outputs update im-

mediately after

BUSY goes high. The user may hold the LDAC input permanently low and in this case the DAC outputs

update immediately after

BUSY goes high. BUSY also goes low during power-on-reset and when a falling edge is de-

tected on the

RESET pin . During this time all interfaces are disabled and any events on LDAC are ignored.

The AD5380 contains an extra feature whereby a DAC register is not updated unless it’s x2 register has been written to

sincethe last time

LDAC was brought low. Normally, when LDAC is brought low, the DAC registers are filled with the

contents of the x2 registers. However the AD5380 will only update the DAC register if the x2 data has changed, thereby

removing unnecessary digital crosstalk.

FIFO Operation in Parallel mode

The AD5380 contains a FIFO to optimize operation when operating in parallel interface mode. The FIFO Enable

(level sensitive active high)is uesed to enable the internal FIFO. When connected to DVCC the internal FIFO is en-

abled allowing the user to write to the device at full speed. FIFO is only available in parallel interface mode. The status

of the FIFO_EN pin is sampled on power-up, and also following a CLEAR or RESET to determine if the FIFO is

enabled. In either serial or I2C interface modes the FIFO_EN pin shpould be tied low. Up to 128 successive intructions

can be written to the FIFO at maximum speed in parallel mode. When the FIFO is full any further writes to the device

are ignored. Figure 9 shows a comparisson between FIFO mode and non-FIFO mode in terms of channel update time,

diguial loading time is also outlined in this graph.

0.00E+00

5.00E-06

1.00E-05

1.50E-05

2.00E-05

2.50E-05

1

4

7

10 13 16 19 22 25 28 31 34 37 40

Number of Writes

Without FIFO (Channel

update time)

With FIFO (Channel update

time)

With FIFO (digital loading

time)

Figure 8. Channel Update Rate (FIFO vs NON-FIFO)