PRELIMINARY TECHNICAL DATA

REV. PrF 09/2003

–18–

AD5380

AD5380 On-chip Special Function Registers (SFR)

The AD5380 contains a number of special function registers (SFRs)as outlined in table V. SFRs are addressed with

REG1=REG0= 0 and are decoded using the Address bits A5 to A0.

Table V. SFR Register Functions (REG1 =0, REG0 = 0)

R/

W

W

W

W

W A5 A4 A3 A2 A1

A0

Function

X

00000

0

NOP (No Operation)

0

00000

1

Write ClR Code

0

00001

0

Soft CLR

0

00100

0

Soft Power Down

0

00100

1

Soft Power Up

0

00110

0

Control Register Write

1

00110

0

Control Register Read

0

00101

0

Monitor Channel

0

00111

1

Soft Reset

SFR Commands

NOP (no operation)

REG1=REG0=0, A5-A0=000000

Performs no operation but is useful in readback mode to clock out data on Dout for diagnostic purposes.

BUSY pulses

low during a NOP operation.

Write CLR Code

REG1=REG0=0, A5-A0=000001

DB13-DB0= Contain the CLR data.

Bringing the

CLR line low or exercising the soft clear function will load the contents of the DAC registers with the data

contained in the user configurable CLR register and sets VOUT0-VOUT39 accordingly. This can be very useful not

only for setting up a specific output voltage in a clear condition but can also be used for calibration purposes where the

user can load fullscale or zeroscale to the the clear code register and then issue a hardware or software clear to load this

code to all DAC removing the need for individual writes to all DACs. Default on power up is all zeroes.

Soft CLR

REG1=REG0=0, A5-A0=000010

DB13-DB0= Dont Care.

Executing this instruction performs the CLR which is functionally the same as that provided by the external CLR pin.

The DAC outputs are loaded with the data in the CLR code register. The time taken to fully execute the SOFT CLR is

80*400ns and is indicated by the

BUSY low time.

Soft Power Down

REG1=REG0=0, A5-A0=001000

DB13-DB0= Dont Care.

Executing this instruction performs a global power-down feature that puts all channels into a low power mode reducing

both analog and digital power consumption to 5uA. In power down mode the output amplifier can be configured as a

high impedance output or provide a 100k load to ground. The contents of all internal registers are retained in power-

down mode. Cannot write to any register while in power down.

Soft Power up

REG1=REG0=0, A5-A0=001001

DB13-DB0= Dont Care.

This instruction is used to power up the output amplifiers and internal reference. The time to exit power down is XXus.

The hardware power down and software function are internally combined in a digital OR function.

Soft RESET

REG1=REG0=0, A5-A0=001111

DB13-DB0= Dont Care.

This instruction is used to implement a software reset. All internal registers are reset to their default values which corre-

sponds to m at fullscale and c at zero. The contents of the DAC registers are cleared setting all analog outputs to zero

volts. The soft reset activation time is 150us (typ).