CS42516 datasheet(27/90 Pages) CIRRUS

27 / 90 page

DS583F1

CS42516

When either serial port is in Slave Mode, its respective LRCK signal must be present for proper device

operation.

In Slave Mode, One-Line Mode #1 is supported; One-Line Mode #2 is not.

The sample rate to OMCK ratios and OMCK frequency requirements for Slave Mode operation are shown

in Table 1. Refer to Table 3 for required clock ratios.

4.6

Digital Interfaces

4.6.1

Serial Audio Interface Signals

The CS42516 interfaces to an external Digital Audio Processor via two independent serial ports, the

CODEC serial port, CODEC_SP and the Serial Audio Interface serial port, SAI_SP. The digital output of

the internal ADCs can be configured to use either the CX_SDOUT pin or the SAI_SDOUT pin and the

corresponding serial port clocking signals. These configuration bits and the selection of Single-, Double-

or Quad-Speed Mode for CODEC_SP and SAI_SP are found in register “Functional Mode (address 03h)”

on page 48.

The serial interface clocks, SAI_SCLK for SAI_SP and CX_SCLK for CODEC_SP, are used for transmit-

ting and receiving audio data. Either SAI_SCLK or CX_SCLK can be generated by the CS42516 (Master

Mode), or it can be input from an external source (Slave Mode). Master or Slave Mode selection is made

using bits CODEC_SP M/S and SAI_SP M/S in register “Misc Control (address 05h)” on page 51.

The Left/Right clock (SAI_LRCK or CX_LRCK) is used to indicate left and right data frames and the start

of a new sample period. It may be an output of the CS42516 (Master Mode), or it may be generated by

an external source (Slave Mode). As described in later sections, particular modes of operation do allow

the sample rate, Fs, of the SAI_SP and the CODEC_SP to be different, but must be multiples of each

other.

The serial data interface format selection (Left/Right-Justified, I²S or One-Line Mode) for the Serial Audio

Interface serial port data out pin, SAI_SDOUT, the CODEC serial port data out pin, CX_SDOUT, and the

CODEC input pins, CX_SDIN1:3, is configured using the appropriate bits in the register “Interface For-

mats (address 04h)” on page 50. The serial audio data is presented in two's complement binary form with

the MSB first in all formats.

CX_SDIN1, CX_SDIN2, and CX_SDIN3 are the serial data input pins supplying the associated internal

DAC. CX_SDOUT, the ADC data output pin, carries data from the two internal 24-bit ADCs and, when

configured for one-line mode, up to four additional ADC channels attached externally to the signals

ADCIN1 and ADCIN2 (typically two CS5361 stereo ADCs). When operated in One-Line Mode, 6 channels

of DAC data are input on CX_SDIN1 and 6 channels of ADC data are output on CX_SDOUT. Table 4 on

page 28 outlines the serial port channel allocations.

Single-Speed

Double-Speed

Quad-Speed

One-Line Mode #1

OMCK/LRCK Ratio

256x, 384x, 512x

128x, 192x, 256x

64x, 96x, 128x

256x

SCLK/LRCK Ratio

32x, 48x, 64x, 128x

32x, 48x, 64x

128x

Table 3. Slave Mode Clock Ratios

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