CS42516 datasheet(77/90 Pages) CIRRUS

77 / 90 page

DS583F1

CS42516

10.APPENDIX C: PLL FILTER

The PLL has been designed to only use the preambles of the S/PDIF stream to provide lock update information to

the PLL. This results in the PLL being immune to data-dependent jitter effects because the S/PDIF preambles do

not vary with the data.

The PLL has the ability to lock onto a wide range of input sample rates with no external component changes. The

nominal center sample rate is the sample rate that the PLL first locks onto upon application of an S/PDIF data

stream.

10.1

External Filter Components

10.1.1

General

The PLL behavior is affected by the external filter component values and the locking mode as configured

by the LOCKM[1:0] bits in register 24h. Table 21 shows the supported configurations of PLL component

values and their associated locking modes.

Phase

Com parator

and Charge Pum p

÷N

VCO

RM CK

INPUT

CRIP

CFILT

RFILT

Figure 27. PLL Block Diagram

RFILT (k

Ω)CFILT (µF) CRIP (pF) LOCKM[1:0]

Notes

Configuration 1

2.55

0.047

2200

Used for backward compatibility with Revision C

devices.

Configuration 2

2.55

0.047

2200

Default configuration for Revision D devices.

Provides improved wideband jitter rejection in

Double- and Quad-Speed modes.

Configuration 3

1.37

0.022

1000

Provides improved in-band jitter rejection, with

increased wideband jitter. Use this configuration

for best DAC and ADC performance when

clocked from the PLL recovered clock.

Table 21. External PLL Component Values & Locking Modes

CS42516 датащи(PDF) 77 Page - Cirrus Logic

CS42516 датащи(HTML) 77 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90

датащи скачать

ссылки URL