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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AD9154-EBZ датащи(PDF) 27 Page - Analog Devices |
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AD9154-EBZ датащи(HTML) 27 Page - Analog Devices |
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27 / 124 page  Data Sheet AD9154 Rev. C | Page 27 of 124 Addr. Bit No. Value1 Variable Description 0x459 0x [7:5] JESDVer JESDVer = 1 for JESD204B, JESDVer = 0 for JESD204A. [4:0] S − 12 See the JESD204B Setup section. 0x45A 7 0x HD See the JESD204B Setup section. [4:0] CF CF = 0 0x45D 0x Lane0Checksum See the JESD204B Setup section. 0x46C 0x Lanes Deskew lanes. 0x476 0x F See the JESD204B Setup section. 0x47D 0x Lanes Enable lanes. See the JESD204B Setup section. 1 0x denotes a register value that the user must fill in. See the Variable and Description columns for information on selecting the appropriate register value. 2 This JESD204B link parameter is programmed in n − 1 notation as noted. For example, if the setup requires L = 8 (8 lanes per link), program L − 1 or 7 into Register 0x453, Bits[4:0]. If using dual link, perform writes from Register 0x300 to Register 0x47D with CurrentLink = 0, and then repeat the same set of register writes with CurrentLink = 1. Write to Register 0x200 and Register 0x201 only once. STEP 4: PHYSICAL LAYER This section describes how to set up the physical layer of the SERDES interface. In this section, the input termination settings are configured along with the CDR sampling and SERDES PLL. Table 21. Device Configurations and Physical Layer Settings Addr. Bit No. Value1 Variable Description 0x2A7 0x01 Autotune PHY setting 0x2AE 0x01 Autotune PHY setting 0x314 0x01 SERDES SPI configuration 0x230 0x 5 Halfrate Set up the CDR; see the SERDES Clocks Setup section [4:2] 0x2 [2:1] OvSmp Set up the CDR; see the SERDES Clocks Setup section 0x206 0x00 Reset the CDR 0x206 0x01 Release the CDR reset 0x289 0x 2 1 SERDES PLL configuration [1:0] PLLDiv Set the CDR oversampling for PLL; see the SERDES Clocks Setup section 0x284 0x62 Optimal SERDES PLL loop filter 0x285 0xC9 Optimal SERDES PLL loop filter 0x286 0x0E Optimal SERDES PLL loop filter 0x287 0x12 Optimal SERDES PLL CP 0x28A 0x7B Optimal SERDES PLL VCO LDO 0x28B 0x00 Optimal SERDES PLL PD 0x290 0x89 Optimal SERDES PLL VCO 0x291 0x4C Optimal SERDES PLL VCO 0x294 0x24 Optimal SERDES PLL CP 0x296 0x1B Optimal SERDES PLL VCO 0x297 0x0D Optimal SERDES PLL VCO 0x299 0x02 Optimal SERDES PLL PD 0x29A 0x8E Optimal SERDES PLL VCO 0X29C 0x2A Optimal SERDES PLL CP 0x29F 0x7E Optimal SERDES PLL VCO 0x2A0 0x06 Configure SERDES PLL VCO 0x280 0x01 Enable SERDES PLL2 0x268 0x [7:6] EqMode See the Equalization Mode Setup section [5:0] 0x22 Required value (default) 1 0x denotes a register value that the user must fill in. See the Variable and Description columns for information on selecting the appropriate register value. 2 Verify that Register 0x281, Bit 0 reads back 1 after enabling the SERDES PLL to indicate that the SERDES PLL has locked. |
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