AD9154-EBZ datasheet(60/124 Pages) AD

60 / 124 page

AD9154

Data Sheet

Rev. C | Page 60 of 124

Monitoring Errors via SYNCOUTx±

When one or more disparity, not in table, or unexpected

control character error occurs, the error is reported on the

SYNCOUTx± pins as per Section 7.6 of the JESD204B

specification. The JESD204B specification states that

the SYNCOUTx± signal is asserted for exactly 2 frame periods

when an error occurs. For the AD9154, the width of

the SYNCOUTx± pulse can be programmed. The settings to

achieve a SYNCOUTx± pulse of 2 frame clock cycles are given in

Table 60.

Table 60. Setting SYNCOUTx± Error Pulse Duration

These register settings assert the SYNCOUTx± signal for 2 frame clock cycles

pulse widths.

Disparity, NIT, Unexpected Control Character IRQs

For disparity, not in table, and unexpected control character

errors, error count over the threshold events are available as

IRQ events. Enable these events by writing to Register 0x47A,

Bits[7:5]. The IRQ event status can be read at the same address

(Register 0x47A, Bits[7:5]) after the IRQs are enabled.

Errors Requiring Reinitializing

A link reinitialization automatically occurs when four invalid

disparity characters are received as per Section 7.1 of the JESD

specification. When a link reinitialization occurs, the resync

request is 5 frames and 9 octets long.

The user can optionally reinitialize the link when the error

count for disparity errors, not in table errors, or unexpected

control characters reaches a programmable error threshold. The

process to enable the reinitialization feature for certain error

types is as follows:

1. Set THRESHOLD_MASK_EN (Register 0x477, Bit 3) = 1.

Note that when this bit is set, unmasked errors do not

saturate at either threshold or maximum value.

2. Enable the sync assertion mask for each type of error by

writing to the SYNC_ASSERTION_MASK register

(Register 0x47B, Bits[7:5]) according to Table 61.

3. Program the desired error counter threshold into

ERRORTHRES (Register 0x47C).

4. For each error type enabled in the SYNC_ASSERTION_

MASK register, if the error counter on any lane reaches the

programmed threshold, SYNCOUTx± falls, issuing a sync

request. Note that all error counts are reset when a link

reinitialization occurs. The IRQ does not reset and must be

reset manually.

Table 61. Sync Assertion Mask

Addr.

Bit No.

Bit Name

Description

0x47B

BADDIS_S

Set to 1 to assert SYNCOUTx±

if the disparity error count

reaches the threshold

NIT_S

Set to 1 to assert SYNCOUTx±

if the not in table error count

reaches the threshold

UCC_S

Set to 1 to assert SYNCOUTx±

if the unexpected control

character count reaches the

threshold

CGS, Frame Sync, Checksum, and ILAS Monitoring

that each stage of JESD204B link establishment has occurred.

Program Register 0x300, Bit 2 = 0 to monitor the status of the

lanes on Link 0, and Register 0x300, Bit 2 = 1 to monitor the

status of the lanes on Link 1.

Bit x of CODEGRPSYNCFLAG (Register 0x470) is high if

Link Lane x received at least 4 K28.5 characters and passed code

group synchronization.

Bit x of FRAMESYNCFLAG (Register 0x471) is high if

Link Lane x completed initial frame synchronization.

Bit x of GOODCHKSUMFLG (Register 0x472) is high if the

checksum sent over the lane matches the sum of the JESD204B

parameters sent over the lane during ILAS for Link Lane x. The

parameters can be added either by summing the individual fields

in registers or summing the packed register. If Register 0x300,

Bit 6 = 0 (default), the calculated checksums are the lower 8 bits

of the sum of the following fields: DID, BID, LID, SCR, L − 1, F − 1,

K − 1, M − 1, N − 1, SUBCLASSV, NP − 1, JESDV, S − 1, and

HD. If Register 0x300, Bit 6 = 1, the calculated checksums are

the lower 8 bits of the sum of Register 0x400 to Register 0x40C

and LID.

Bit x of INITIALLANESYNC (Register 0x473) is high if

Link Lane x passed the initial lane alignment sequence.

CGS, Frame Sync, Checksum, and ILAS IRQs

Fail signals for CGS, frame sync, checksum, and ILAS are available

as IRQ events. Enable them by writing to Register 0x47A,

Bits[3:0]. The IRQ event status can be read at the same address

(Register 0x47A, Bits[3:0]) after the IRQs are enabled. Write a 1

to Register 0x470, Bit 7 to reset the CGS IRQ. Write a 1 to

JESD204B

Mode IDs

PClockFactor

(Frames/PClock)

SYNCB_ERR_DUR

(Register 0x312[5:4]) Setting1

0, 4, 9

0 (default)

1, 2, 5, 6, 10

3, 7

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