AD9154-EBZ datasheet(96/124 Pages) AD

96 / 124 page

AD9154

Data Sheet

Rev. C | Page 96 of 124

Addr.

Name

Bits

Bit Name

Settings

Description

Reset

Access

[3:0]

SYNCMODE

Sync Mode.

0x0

R/W

0 Reserved.

1 Sync one-shot mode.

2 Sync continuous mode.

5 Reserved.

6 Reserved.

8 Sync monitor only mode.

A Sync one-shot then monitor.

9 Sync one-shot then monitor.

D Reserved..

E Reserved

0x03B

SYNC_STATUS

REFBUSY

Sync Machine Busy.

0x0

1 Sync logic SM is busy.

[6:4]

RESERVED

Reserved.

0x0

REFLOCK

Sync Alignment Locked.

0x0

1 Sync logic aligned within window.

REFROTA

Sync Rotated.

0x0

1 Sync logic rotated with SYSREF± (sticky).

REFWLIM

Sync Alignment Limit Range.

0x0

1 Phase error outside of specified window error threshold.

REFTRIP

Sync Tripped After Arming.

0x0

1 Sync received SYSREF pulse (sticky).

0x03C

SYNC_

CURRERR_L

[7:0]

CURRERROR_L

Sync Alignment Error. This register gives the user real

time access of the SYSREF± to the internal clock

counters. The value of SYNC_CURRERR =

(SYNC_CURRERR_H[0],SYNC_CURRERR_L) is the

difference between the SYSREF± position relative to

the clock divider and the target position relative to

the internal counter. This register monitors the phase

of the internal clocks in monitor modes of operation.

If an adjustment of the clocks is made on any given

SYSREF±, the value of the phase error is placed into

SYNC_LASTERR and SYNC_CURRERR is forced to 0.

0x0

0x03D

SYNC_

CURRERR_H

CURRUNDER

Sync Current Error Under Flag.

0x0

1 Current phase error under window tolerance.

CURROVER

Sync Current Error Over Flag.

0x0

1 Current phase error over window tolerance.

[5:1]

RESERVED

Reserved.

0x0

CURRERROR_H

Sync Current Error[8].

0x0

0x040

DAC_GAIN0_I

[7:2]

RESERVED

Reserved.

0x0

[1:0]

DAC_GAIN_I1

I DAC Current Scaling MSBs

0x3

R/W

0x041

DAC_GAIN1_I

[7:0]

DAC_GAIN_I0

I DAC Current Scaling LSBs.

0xFF

R/W

0x042

DAC_GAIN0_Q

[7:2]

RESERVED

Reserved.

0x0

[1:0]

DAC_GAIN_Q1

Q DAC Current Scaling MSBs.

0x3

R/W

0x043

DAC_GAIN1_Q

[7:0]

DAC_GAIN_Q0

Q DAC current scaling LSBs.

0xFF

R/W

0x044

GROUPDELAY

COMP_I

[7:0]

GROUP DELAY

COMP I [7:0]

Group Delay Compensation Bits for I Channel. These

bits set the group delay compensation for the

I channel DAC.

0x0

R/W

0x045

GROUPDELAY

COMP_Q

[7:0]

GROUP DELAY

COMP Q [7:0]

Group Delay Compensation Bits for Q Channel. These

bits set the group delay compensation for the Q

channel DAC.

0x0

R/W

0x046

GROUPDELAY

COMP_BYP

[7:2]

RESERVED

Reserved.

0x0

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