AD9154-EBZ datasheet(58/124 Pages) AD

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AD9154

Data Sheet

Rev. C | Page 58 of 124

JESD204B TEST MODES

PHY PRBS Testing

The JESD204B receiver on the AD9154 includes a pseudorandom

binary sequence (PRBS) pattern checker on the back end of its

physical layer. This functionality enables bit error rate (BER)

testing of each physical lane of the JESD204B link. The PHY

PRBS pattern checker does not require that the JESD204B link be

established. It can synchronize with a PRBS7, PRBS15, or PRBS31

data pattern. PRBS pattern verification can be performed on

multiple lanes at once. The error counts for failing lanes are

reported for one JESD204B lane at a time. The process for

performing PRBS testing on the AD9154 is as follows:

1. Start sending a PRBS7, PRBS15, or PRBS31 pattern from

the JESD204B transmitter.

2. Select and write the appropriate PRBS pattern to

3. Enable the PHY test for all lanes being tested by writing to

PHY_TEST_EN (Register 0x315). Each bit of Register 0x315

enables the PRBS test for the corresponding lane. For

example, writing a 1 to Bit 0 enables the PRBS test for

Physical Lane 0.

4. Toggle PHY_TEST_RESET (Register 0x316, Bit 0) from 0

to 1, then back to 0.

5. Set PHY_PRBS_ERROR_THRESHOLD (Register 0x319 to

6. Write a 0 and then a 1 to PHY_TEST_START

(Register 0x316, Bit 1). The rising edge of

PHY_TEST_START starts the test.

7. Wait 500 ms.

8. Stop the test by writing 0 to PHY_TEST_START

(Register 0x316, Bit 1).

9. Read the PRBS test results.

a. Each bit of PHY_PRBS_TEST_STATUS (Register

0x31D) corresponds to one SERDES lane. 0 = fail,

1 = pass.

b. The number of PRBS errors seen on each failing lane

can be read by writing the lane number to check (0 to

7) in the PHY_SRC_ERR_CNT (Register 0x316,

Bits[6:4]) and reading PHY_PRBS_ERR_COUNT

(Register 0x31A to Register 0x31C). The maximum

error count is 224− 1. If all bits of Register 0x31A to

the selected lane has been exceeded.

Table 57. PHY PRBS Pattern Selection

PHY_PRBS_PAT_SEL Setting

(Register 0x316[3:2])

PRBS Pattern

0b00 (default)

PRBS7

0b01

PRBS15

0b10

PRBS31

Transport Layer Testing

The JESD204B receiver in the AD9154 supports the short

transport layer (STPL) test as described in the JESD204B

standard. Use this test to verify the data mapping between the

JESD204B transmitter and receiver.

The STPL test ensures that each sample from each converter is

mapped appropriately according to the number of converters

(M) and the number of samples per converter (S). As specified

in the JESD204B standard, the converter manufacturer specifies

what test samples are transmitted. Each sample must have a

unique value. For example, if M = 2 and S = 2, four unique

samples are transmitted repeatedly until the test is stopped. The

expected sample must be programmed into the device and the

expected sample is compared to the received sample one sample

at a time until all have been tested. The process for performing

this test on the AD9154 is described as follows:

1. Synchronize the JESD204B link.

2. Enable the STPL test at the JESD204B Tx.

3. Select Converter 0 Sample 0 for testing. Write

SHORT_TPL_M_SEL (Register 0x32C, Bits[3:2]) = 0 and

SHORT_TPL_SP_SEL (Register 0x32C, Bits[5:4]) = 0.

4. Set the expected test sample for Converter 0, Sample 0.

Program the expected 16-bit test sample into the

SHORT_TPL_REF_SP_x registers (Register 0x32E and

5. Enable the STPL test. Write 1 to SHORT_TPL_TEST_EN

(Register 0x32C, Bit 0).

6. Toggle the STPL reset, SHORT_TPL_TEST_RESET

(Register 0x32C, Bit 1), from 0 to 1, then back to 0.

7. Check for failures. Read SHORT_TPL_FAIL

(Register 0x32F, Bit 0), 0 = pass, 1 = fail.

8. Repeat Steps 3 to Step 7 for each sample of each converter.

Conv0Sample0 through ConvM− 1SampleS − 1.

Repeated CGS and ILAS Test

As per Section 5.3.3.8.2 of the JESD204B specification, the

AD9154 can check that a constant stream of /K28.5/ characters

is being received, or that a CGS followed by a constant stream of

ILAS is being received.

To run a repeated CGS test, send a constant stream of /K28.5/

characters to the AD9154 SERDES inputs. Next, set up the

device and enable the links as described in the Device Setup

Guide section. Ensure that the /K28.5/ characters are being

received by verifying that the SYNCOUTx± signal has been

deasserted and that CGS has passed for all enabled link lanes by

reading Register 0x470. Program Register 0x300, Bit 2 = 0 to

monitor the status of lanes on Link 0, and Register 0x300, Bit 2 = 1

to monitor the status of lanes on Link 1 for dual link mode.

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