IX6610 datasheet(20/23 Pages) IXYS

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PRELIMINARY

R00A

IX6610

2.1.13 3.3V LDO Regulator (VDD)

The LDO regulator provides 3.3V power to the

external MCU and most of the IX6610 internal circuits.

LDO is sourced from the VAUX pin, and powers up

along with the startup regulator (VCC). LDO is

designed for a fixed external load capacitor with a

predetermined ESR range.

To use the MODE control for an external VDD the

external power supply should be connected to the

3.3V VDD output pin only after the IX6610 starts with

its internal power supply and MODE pin is set logic

HIGH with current limiting resistor (~1k

) to prevent

powering logic from a signal source.

Notes on MODE feature to shut down the internal VDD

regulator:

• To avoid overstress to the device, it is recommended

to allow the internal regulators to power up prior to

connecting an external power supply via the MODE

feature.

• The external supply should not exceed V

CC (4.1V)

• The following diagram shows the device connections

of the internal regulator pass devices.

2.1.14 Dead Time Delay Capacitor Selection

Ceramic capacitors are recommended for CA and CB

dead time capacitors. They should be located as close

as possible to the pins and connected to a low noise

ground.

2.1.15 RESET

A Logic high level at the external reset pin disables the

power converter, the LDO, initiates power converter

startup sequence, and resets the fault flags. Holding

RESET low for sufficient time will lower the LDO

voltage to a level that may initiate a POR sequence in

the MCU. The RESET pin has an internal 20k

 pull

down resistor.

2.1.16 TEST

The TEST pin should be tied to ground.

IN=15V

AUX

~ 4.1V

~ 3.3V

MODE

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