IX6610 datasheet(18/23 Pages) IXYS

18 / 23 page

PRELIMINARY

R00A

IX6610

2.1.2

Short Pulse Filter

A narrow pulse detector is implemented in the IX6610

to prevent transmission of very narrow false PWM

input signals to the IGBT drivers due to noise coupling

at the input pins. Input signal pulse widths narrower

than 100ns will be suppressed and pulse widths

greater than 350ns will be transferred to the IGBT

drivers.

2.1.3

Dead Time Generator

In the half bridge driver configuration, dead time needs

to be added to the incoming input signals to prevent

shoot through due to overlap of the high side and low

side drivers. The required dead time is programmed

by the external MCU.

The IX6610 also contains a dead time circuit that adds

dead time to the input signals INA and INB after the

input signal interlock function. This dead time applies

only if the programmed MCU dead time is shorter than

the IX6610 dead time. The IX6610 dead time can be

programmed by changing the external capacitors at

the CA and CB terminals. Figure 1 shows the dead

time insertion.

2.1.4

Oscillator

The IX6610 includes a 200kHz internal oscillator

circuit that provides a 100kHz, 47% duty cycle clock to

the power converter control circuit. The oscillator

circuit provides the necessary high frequency clock

signals to the watchdog timer. The power converter

begins operation using the internal oscillator, and

switches over to the MCU CLK input once it has

detected a valid clock. Note that if the MCU CLK

stops, then the power converter will be clocked by the

internal oscillator. Figure 3 shows the relationship of

external CLK to the power converter clock. Duty cycle

of CLK pin input determines the duty cycle of the

power converter operation using the following formula:

2.1.5

Under Voltage Lockout

The Under Voltage Lockout (UVLO) circuit holds both

PWM logic control signals INA and INB low during the

VIN supply ramp-up. When the supply voltage rises

above the UVLO upper threshold, the UVLO circuit

allows the PWM inputs to control the drivers. FAULT1

output is driven high during the UVLO condition.

Figure 8 illustrates the UVLO function.

2.1.6

Over Voltage Lockout

The over voltage lockout (OVLO) circuit holds both

PWM logic control signals INA and INB low and

disables the power converter control block during any

VIN over voltage condition. When VIN supply voltage

falls below the OVLO threshold, the OVLO circuit

allows the PWM inputs to control the drivers and

enables the power converter control block. FAULT1

and FAULT2 outputs are driven high during the OVLO

condition. Figure 9 illustrates the OVLO function.

2.1.7

Signal Transformer Primary Switches and Pulse

Generators

The signal transformer primary terminals are

connected to high current switches. Gate drive to the

high current switches is controlled by the logic input

signals INA and INB, which, when active, produce a

high current pulse on the rising edge and falling edge

of the input signals at the TRAP (TRBP) and TRAN

(TRBN) outputs respectively. Narrow pulses are used

to drive the transformer switches, see Figure 1.

2.1.8

Signal Transformer Secondary Receive Inputs and

Fault Detect

The IX6610 has four single ended receiver

comparators which sense the presence of signals that

are more positive than a fixed positive threshold value.

A 1k

 pull down resistor to ground is connected to

each of the receiver inputs. An external low pass filter

can be implemented to prevent impulse noise from

triggering the receivers. Receiver comparators are

high speed Schmitt Trigger buffers with 1V typical

hysteresis.

Secondary side power supply faults and IGBT power

stage faults are transmitted back to the IX6610

(primary side) through a pulse transformer. The

FAULT1 output is used to signal power supply under

voltage fault events on either the secondary side or the

primary side. The FAULT2 output is used to signal a

secondary side power stage fault. FAULT1 and

FAULT2 outputs together signal primary and

secondary side over voltage fault events.

Primary side and secondary side power supply faults

are latched, and fault flags are asserted logic high.

If the FAULT1 and FAULT2 flags are set by primary

side power supply or over-temp faults, then the input

signals to the secondary side drivers are disabled.

When the device recovers from the primary side

power supply faults, the auto restart feature or external

DutyCycleDC_CLK

0.5

DutyCycleCLK

2.015

-------------------------------------

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