HTADC12 datasheet(10/12 Pages) HONEYWELL

10 / 12 page

Symbol

Parameter

Min.

Typ.

Max.

Units

STS Delay After Data Buffer Turn-On

110

Rising Edge of First Clock

Data Output Formats: There are three output formats:

12 bit parallel, two 8 bit parallel, and serial.

28 Pin Package: The parallel data can be presented as either

12 straight binary bits or configured for a “two-byte READ”

for use with 8 bit processor busses.

12-Bit Data Readout in 8-Bit Systems: The HTADC12’s

12-bit parallel data output can be read out by an 8-bit system

in two 8-bit bytes. In this mode, the 8 MSB bit positions of

the 12-bit output are utilized as the 8-bit bus.

Address control of the byte of interest is handled by the logic

state of the A0 control line.

• When A0=0, the output data assumes its normal 12-bit format

with bits D11-D4 of the 12-bit word forming the 1st data byte.

• When A0=1, bits D3-D0 followed by 4 logic zeroes are

superimposed onto the 8 MSB bit positions, forming

the 2nd data byte.

Serial Output Control (14 Pin Package): Conversions in the

serial output mode are initiated identically to the parallel output

mode described above. The serial data output, SDO, is enabled

identically as well.

Valid data becomes available at SDO immediately at the end of

the conversion cycle (slightly prior to STS). Data is output MSB

first, and advances one bit position with each SCLK falling edge.

Rising SCLK edges may be used to clock serial data into

the master.

SCLK activity occurring other than when SDO is properly

enabled for read is ignored.

Data Output

Data Output Values

Pins

AO = 0

AO = 1

(READ bits D4 – D11) (READ bits D0 – D3)

D11

D10

“0”

8 Bit Bus

Serial Output Timing Diagram

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