поискавой системы для электроныых деталей
  Russian  ▼
ALLDATASHEETRU.COM

X  

Preview PDF HTML

HTADC12 датащи(PDF) 9 Page - Honeywell Solid State Electronics Center

номер детали HTADC12
подробное описание детали  High Temperature 12-Bit A/D Converter
PDF  12 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
производитель  HONEYWELL [Honeywell Solid State Electronics Center]
домашняя страница  http://honeywell.com/Pages/Home.aspx
Logo HONEYWELL - Honeywell Solid State Electronics Center

HTADC12 датащи(HTML) 9 Page - Honeywell Solid State Electronics Center

Back Button HTADC12 Datasheet HTML 4Page - Honeywell Solid State Electronics Center HTADC12 Datasheet HTML 5Page - Honeywell Solid State Electronics Center HTADC12 Datasheet HTML 6Page - Honeywell Solid State Electronics Center HTADC12 Datasheet HTML 7Page - Honeywell Solid State Electronics Center HTADC12 Datasheet HTML 8Page - Honeywell Solid State Electronics Center HTADC12 Datasheet HTML 9Page - Honeywell Solid State Electronics Center HTADC12 Datasheet HTML 10Page - Honeywell Solid State Electronics Center HTADC12 Datasheet HTML 11Page - Honeywell Solid State Electronics Center HTADC12 Datasheet HTML 12Page - Honeywell Solid State Electronics Center  
Zoom Inzoom in Zoom Outzoom out
 9 / 12 page
background image
Closed Loop – Processor Controlled
This mode requires control the input enable pins CE, NCS, and
RNC. The STS signal will be used to notify the processor that a
conversion is complete. The processor then changes the state
of RNC to read the output data.
Assuming that CE is high and NCS is low, a typical conversion
sequence might thus be:
(1) CE and NCS are set to activate the device.
(2) RNC is then changed from a high to a low value which
starts the conversion.
Symbol
Parameter
Min.
Typ.
Max.
Units
T7
Setup Time NCS To RNC
0
5
ns
T6
Setup Time CE To RNC
0
5
ns
T1
STS Delay From RNC
100
ns
T3
Conversion Time
9
10
11.5
µs
T8
READ Delay After Enable
20
ns
T5
High Z Delay After Disable
20
ns
(3) The STS signal will then go to a high value.
(4) When the conversion is complete, STS will go low.
This will be detected by the processor/controller.
(5) The controller then sets RNC back to a high level and the
signaling the data can be read at the outputs.
(6) Following the read, CE and NCS are then set to disable the
device and putting the outputs into a high impedance state.
9
Closed Loop Timing Diagram



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12


датащи скачать

Go To PDF Page


ссылки URL



Вашему бизинису помогли Аллдатащит?  [ DONATE ] 

Что такое Аллдатащит   |   реклама   |   контакт   |   Конфиденциальность   |   Ссылка на техническое описание    |   обмен ссыками   |   поиск по производителю
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com