(1) Unless otherwise specified, specifications apply over the full operating temperature range from -55°C to 225°C,

VDDA externally connected to VDD = 5V, VSSA externally connected to VSS = 0V.

(2) Guaranteed by design.

(3) Maximum serial clock frequency listed is for a 10pF load on SDOUT. For greater capacitive loads,

a lower clock frequency must be used. For Cload = 100pF, Fsclk = 10 MHz is the recommended maximum.

(4) VREF_OUT can provide source current only.

(5) 28 Lead: This device is tested with an EXTERNAL Voltage Reference and therefore the reference is stable over temperature.

Total Error = ADC error

14 Lead: This device uses the INTERNAL Voltage Reference and therefore impacts the overall FS TC of the ADC.

Total Error = ADC error + Voltage Ref error

6

Electrical Performance Characteristics

Symbol

Parameter

Conditions1

Limits:

Min.

Typ.

Max.

Units

# of Bits

Resolution2

12

Bits

INL

Integral Non-Linearity

-2.8

+2.8

LSB

DNL

Differential Non-Linearity

28 Lead Package

-1.0

+1.8

LSB

14 Lead Package

-1.0

+1.96

LBS

Offset

Offset Error

VIN value @ VOUT=Voltage equivalent to

-5

0

+5

LSB

0.0 (from Linear regression) LSB, T=25°C

OS_TC

Offset Error Tempco

VIN value @ VOUT=Voltage equivalent to

-5

+5

ppm/°C

0.0 (from Linear regression) LSB, T=25°C

FS_ERR

Full Scale Calibration Error

Maximum Change in Full Scale Calibration -0.3

+0.3

% of FS

VREFIN = 2.5V, T=25°C

FS_TC

FS Calibration Error Tempco

28 Lead Package5

-3

+3

ppm/°C

Maximum Change in Full Scale Calibration

VREFIN = 2.5V, T=25°C

14 Lead Package5

-7

+7

ppm/°C

Maximum Change in Full Scale Internal

VREFIN = 2.5V +/- 10mV, T=25°C

PSRA

Power Supply Rejection

Magnitude of Output Code

-1

1

LSB

+4.75V ≤ VDDA ≤ 5.25V

PSRD

Power Supply Rejection

Magnitude of Output Code

-1

1

LSB

+4.5V ≤ VDD ≤ 5.5V

VREFOUT

Reference Output Voltage

55°C < T > 255°C

2.49

2.51

V

D

VRO-TIME

VREFOUT Drift with time

T = 255°C, .t = 1000 hours2

-3

+3

mV

D

VRo/DVDDA VREFOUT Line Regulation-DC VDDA = 5V ± 0.25V

-1

+1

mV/V

D

VRO/DIO

VREFOUT Load Regulation-DC 0.0 mA ≤ Iout ≤ +8.0 mA4

0.5

mV/mA

VRN

VREFOUT Noise2

f = 0.1Hz to 10kHz

110

µV rms

TCONV

Conversion Time

9

11.5

µs

FSCLK

Serial Clock Frequency

Cload = 10pF3

40

MHz

TWAKEUP

Wake-up time from NAP

30

µs

(ADC ready to convert)

VOSAA

Auxilliary Amplifier Input

-3

±1

+3

mV

Offset Voltage

BWAA

Auxilliary Amp Unity Gain

Cload = 40pf

3

5

MHz

Bandwidth2

D

R/R

Aux Amp Input Resistor

0.1

+0.1

%

Divider (/2) Matching2