ADF4155BCPZ datasheet(13/32 Pages) AD

13 / 32 page

Data Sheet

ADF4155

INT N Mode

If FRAC1 and FRAC2 = 0, the synthesizer operates in integer-N

mode.

R Counter

The 10-bit R counter allows the input reference frequency, REFIN,

to be divided down to produce the reference clock to the PFD.

Division ratios from 1 to 1023 are allowed.

PHASE FREQUENCY DETECTOR AND CHARGE PUMP

The phase frequency detector takes inputs from the R counter

and N counter and produces an output proportional to the

phase and frequency difference between them. Figure 19 is a

simplified schematic of the phase frequency detector. The PFD

includes a fixed delay element that sets the width of the

antibacklash pulse (ABP), which is typically 2.6 ns. This pulse

ensures that there is no dead zone in the PFD transfer function

and provides a consistent reference spur level.

Figure 19. PFD Simplified Schematic

MUXOUT AND LOCK DETECT

The output multiplexer on the ADF4155 allows the user to access

various internal points on the chip. The state of MUXOUT is

controlled by the M3, M2, and M1 bits in Register 4 (for further

details, see Figure 28). Figure 20 shows the MUXOUT section

in block diagram form.

Figure 20. MUXOUT Schematic

INPUT SHIFT REGISTERS

Data is clocked into the 32-bit shift register on each rising edge

of CLK. The data is clocked in MSB first. Data is transferred

from the shift register to one of the nine latches on the rising

edge of LE.

The destination latch is determined by the state of the four

control bits (C4, C3, C2, and C1) in the shift register. These are

the four LSBs: DB3, DB2, DB1, and DB0, as shown in Figure 2.

The truth table for these bits is shown in Table 5. Figure 22 and

Figure 23 summarize how the latches are programmed.

Table 5. Truth Table for the C4, C3, C2, and C1 Control Bits

Control Bits

PROGRAM MODES

Table 5 and Figure 24 through Figure 32 show how the program

modes must be set up in the ADF4155.

The following ADF4155 settings are double buffered: the

fractional value (FRAC1/FRAC2), the modulus value (MOD2),

the reference doubler, the reference divide by 2 (RDIV2), the

R counter value, the charge pump current setting, and the

R divider select. This means that two events must occur before

the device can use a new value for any of the double buffered

settings. First, the new value must be latched into the device by

writing to the appropriate register. Second, a new write must be

performed on Register R0.

For example, any time that the modulus value is updated,

value is loaded correctly.

DELAY

CHARGE

PUMP

CLR1

HIGH

+IN

HIGH

DOWN

–IN

DGND

DVDD

CONTROL

MUX

MUXOUT

ANALOG LOCK DETECT

DIGITAL LOCK DETECT

R COUNTER OUTPUT

N COUNTER OUTPUT

DGND

RESERVED

THREE-STATE OUTPUT

DVDD

Rev. 0 | Page 13 of 32

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