ADF4155BCPZ datasheet(12/32 Pages) AD

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ADF4155

Data Sheet

CIRCUIT DESCRIPTION

REFERENCE INPUT SECTION

The reference input stage is shown in Figure 17. The reference

input can accept both single-ended and differential signals, and

the choice is controlled by the reference input mode bit (Bit DB30,

this bit must be programmed high. In this case, the SW1 and

SW2 switches are opened, the SW3 and SW4 switches are

closed, and the current source driving the differential pair of the

transistors is switched on. The differential signal is buffered,

before it is fed to the emitter-coupled logic (ECL) to a CMOS

converter. When a single-ended signal is used as the reference,

Bit DB30 in Register 6 must be programmed to 0. In this case,

the SW1 and SW2 switches are closed, the SW3 and SW4

switches are opened, and the current source driving the

differential pair of transistors is switched off.

Figure 17. Reference Input Stage

RF N COUNTER

The RF N counter allows a division ratio in the PLL feedback

path. The division ratio is determined by the INT, FRAC1,

MOD1, FRAC2, and MOD2 values, which build up this divider

(see Figure 18). Note that MOD1 is a fixed nonprogrammable

value equal to 224.

Figure 18. RF N Counter

INT, FRAC, MOD, and R Counter Relationship

The INT, FRAC1, FRAC2, MOD1, and MOD2 values, in

conjunction with the R counter, make it possible to generate

output frequencies that are spaced by fractions of the PFD

frequency (fPFD). For more information, see the RF Synthesizer—

A Worked Example section.

Calculate the RF VCO frequency (RFOUT) by the following:

RFOUT = fPFD × N

(1)

where:

RFOUT is the output frequency of the external VCO voltage

controlled oscillator (without using the output divider).

fPFD is a frequency of phase frequency detector.

N is the desired value of the feedback counter N.

Calculate the fPFD by the following equation:

fPFD = REFIN × [(1 + D)/(R × (1 + T))]

(2)

where:

REFIN is the reference input frequency.

D is the REFIN doubler bit.

R is the preset divide ratio of the binary 10-bit programmable

reference counter (1 to 1023).

T is the REFIN divide by 2 bit (0 or 1)

N comprises

MOD1

MOD2

FRAC2

FRAC1

INT

(3)

where:

INT is the 16-bit integer value (23 to 32,767 for 4/5 prescaler, 75

to 65,535 for 8/9 prescaler).

FRAC1 is the numerator of the primary modulus (1 − 16,777,215).

FRAC2 is the numerator of the 14-bit auxiliary modulus (1 − 16,383).

MOD2 is the programmable, 14-bit auxiliary fractional

modulus (2 − 16,383).

MOD1 is a 24-bit primary modulus with a fixed value of 224

(16,777,216).

This results in a very fine frequency resolution with no residual

frequency error. To apply this formula, take the following steps:

1. Calculate N by dividing RFOUT/fPFD.

2. The integer value of this number forms INT.

3. Subtract this value from the full N value.

4. Multiply the remainder by 224.

5. The integer value of this number forms FRAC1.

6. Calculate the MOD2 basis on the channel spacing (fCHSP) by

MOD2 = fPFD/GCD(fPFD, fCHSP)

(4)

where:

fCHSP is the desired channel spacing frequency.

GCD(fPFD, fCHSP) is a greatest common divider of the PFD

frequency and the channel spacing frequency.

7. Calculate FRAC2 by the following equation:

FRAC2 = [(N − INT) × 224 − FRAC1)] × MOD2

(5)

2.5kΩ

REFIN+

REFIN–

AVDD

BIAS

GENERATOR

BUFFER

85k

Ω

SW2

SW3

SW1

REFERENCE

INPUT MODE

SW4

ECL TO CMOS

BUFFER

R COUNTER

MULTIPLEXER

THIRD-ORDER

FRACTIONAL

INTERPOLATOR

FRAC1

REG

INT

REG

RF N COUNTER

FROM

VCO OUTPUT/

OUTPUT DIVIDERS

TO PFD

N COUNTER

FRAC2

VALUE

MOD2

VALUE

N = INT +

FRAC1 +

MOD1

FRAC2

MOD2

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