ADF4155BCPZ datasheet(7/32 Pages) AD

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Data Sheet

ADF4155

Rev. 0 | Page 7 of 32

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

Mnemonic

Description

CLK

Serial Clock Input. Data is clocked into the 32-bit shift register on the CLK rising edge. This input is a high

impedance CMOS input.

DATA

Serial Data Input. The serial data is loaded MSB first with the four LSBs as the control bits. This input is a high

impedance CMOS input.

Load Enable Input. When LE goes high, the data stored in the shift register is loaded into the register that is

selected by the four LSBs. This input is a high impedance CMOS input.

Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state mode.

A logic high on this pin powers up the device, depending on the status of the power-down bits.

CREG1

Output of Internal Low Dropout (LDO) Regulator. Supply voltage to digital circuits. Nominal voltage of 1.8 V.

100 nF decoupling capacitors to ground required.

Charge Pump Power Supply. VP must have the same or greater value than AVDD up to 5.5 V. Connect

decoupling capacitors, as close to this pin as possible, to the analog ground plane.

CPOUT

Charge Pump Output. When enabled, this output provides ±ICP to the external loop filter. The output of the

loop filter is connected to the VTUNE pin of the external VCO.

CPGND

Charge Pump Ground. This output is the ground return pin for the CPOUT pin.

AVDD

Analog Power Supply. This pin ranges from 3.135 V to 3.465 V. Connect decoupling capacitors, as close to this

pin as possible, to the analog ground plane. AVDD must have the same value as DVDD and RFVDD.

RFIN+

RF Input. This small signal input must be ac-coupled to the external VCO.

RFIN−

Complementary RF Input. Decouple this pin to the ground plane with a small bypass capacitor, typically

100 pF. If driven differentially, connect this input similar to RFIN+.

AGND

Analog Ground. Ground return pins for the analog circuitry.

RFGND

RF Ground. This output is the ground return pin for the RFVDD pin.

RFOUT−

Complementary RF Output. The output level is programmable. The VCO fundamental output or a divided-

down version is available.

RFOUT+

RF Output. The output level is programmable. The VCO fundamental output or a divided-down version is

available.

RFVDD

Analog Power Supply for RF Outputs. This pin ranges from 3.135 V to 3.465 V. Connect decoupling capacitors,

as close to this pin as possible, to the analog ground plane. RFVDD must have the same value as AVDD and DVDD.

PDBRF

RF Power-Down. A logic low on this pin mutes the RF outputs. This function is also software controllable.

DVDD

Digital Power Supply. This pin must be at the same voltage as AVDD and RFVDD. Connect decoupling capacitors,

as close to this pin as possible, to the ground plane.

REFIN+

Reference Input.

REFIN−

Complementary Reference Input.

MUXOUT

Multiplexer Output. The multiplexer output allows the lock detect, the scaled RF, or the scaled reference

frequency to be externally accessed.

CREG1

DATA

CLK

RFGND

RFOUT–

RFOUT+

RFVDD

PDBRF

DVDD

NOTES

1. THE EXPOSED PAD MUST BE CONNECTED

TO GROUND.

ADF4155

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