ADF4155BCPZ datasheet(4/32 Pages) AD

4 / 32 page

ADF4155

Data Sheet

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

Total IDD (DIDD + AIDD + RFIDD)

RF output (Bit DB6, Register 6) disabled,

3.6 GHz at VCO output

105

131

RFOUT+/RFOUT− = 1800 MHz, divide by 2 enabled,

5 dBm

Low Power Sleep Mode

µA

Hardware powered down using CE

500

530

µA

Software powered down, serial peripheral

interface (SPI) powered up in low power sleep

mode

RFOUT+/RFOUT− CHARACTERISTICS

Maximum Output Frequency

4000

MHz

Minimum Output Frequency Using

Dividers

7.8125

MHz

500 MHz fundamental output and

divide by 64 selected

Harmonic Content (Second)

−16

dBc

RFOUT+/RFOUT− = 2.9 GHz, fundamental mode

−26

dBc

RFOUT+/RFOUT− = 2.9 GHz, divide by 2 enabled

Harmonic Content (Third)

−22

dBc

RFOUT+/RFOUT− = 2.9 GHz, fundamental mode

−7

dBc

RFOUT+/RFOUT− = 2.9 GHz, divide by 2 enabled

Minimum RF Output Power1

−4

dBm

Programmable in 3 dB steps

Maximum RF Output Power1

dBm

NOISE CHARACTERISTICS

Negative bleed enabled

Normalized Phase Noise Floor, PNSYNTH2

PLL bandwidth = 500 kHz

Integer-N Mode

−223

dBc/Hz

FRAC = 0

Fractional-N-Mode

−218

dBc/Hz

Normalized 1/f Noise, PN1_f3

−116

dBc/Hz

10 kHz offset; normalized to 1 GHz

In-Band Phase Noise4

−98

dBc/Hz

10 kHz offset from 5.8 GHz carrier

Spurious Signals due to PFD

−110

dBc/Hz

At 5.8 GHz VCO output, fPFD = 61.44 MHz

Frequency

−112

dBc/Hz

At 5.8 GHz VCO output, fPFD = 30.72 MHz

Level of Signal with RF Mute Enabled

−40

dBm

Using an external 18 nH pull-up inductor to RFVDD into a 50 Ω load.

The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 logN (where N is the N counter

value) and 10 logfPFD. PNSYNTH = PNTOT − 10 log fPFD − 20 logN.

The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency (fRF)

and at a frequency offset (f) is given by PN = P1_f + 10log(10kHz/f) + 20log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in the

ADIsimPLL design tool.

fREFIN = 122.88 MHz, fPFD = 61.44 MHz, frequency offset = 10 kHz, VCO frequency = 5.8 GHz, RFOUT = 5.8 GHz, N = 94.40104167, loop bandwidth = 60 kHz, ICP =0. 938 mA,

and IBLEED = 60 µA.

Rev. 0 | Page 4 of 32

ADF4155BCPZ датащи(PDF) 4 Page - Analog Devices

ADF4155BCPZ датащи(HTML) 4 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

датащи скачать

ссылки URL