ADF4153ABCPZ datasheet(18/24 Pages) AD

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ADF4153A

Data Sheet

Rev. A | Page 18 of 24

The programmable modulus is also very useful for multi-

standard applications. If a dual-mode phone requires PDC

and GSM 1800 standards, the programmable modulus is of

great benefit. PDC requires 25 kHz channel step resolution,

whereas GSM 1800 requires 200 kHz channel step resolution.

A 13 MHz reference signal can be fed directly to the PFD. The

modulus is programmed to 520 when in PDC mode (13 MHz/

520 = 25 kHz). The modulus is reprogrammed to 65 for GSM

1800 operation (13 MHz/65 = 200 kHz). It is important that the

PFD frequency remains constant (13 MHz). This lets the user

design one loop filter that can be used in both setups without

running into stability issues. It is the ratio of the RF frequency

to the PFD frequency that affects the loop design. By keeping

this relationship constant, the same loop filter can be used in

both applications.

FASTLOCK WITH SPURIOUS OPTIMIZATION

As mentioned in the Noise and Spur Mode section, the part

can be optimized for spurious performance. However, in fast-

locking applications, the loop bandwidth needs to be wide,

and therefore the filter does not provide much attenuation of

the spurs. The programmable charge pump can be used to get

around this issue. The filter is designed for a narrow-loop

bandwidth so that steady-state spurious specifications are met.

This is designed using the lowest charge pump current setting.

To implement fastlock during a frequency jump, the charge

pump current is set to the maximum setting for the duration of

the jump by asserting the fastlock bit in the N divider register.

This widens the loop bandwidth, which improves lock time. To

maintain loop stability while in wide bandwidth mode, the loop

filter needs to be modified. This is achieved by switching in a

resistor (R1A) in parallel with the damping resistor in the loop

filter (see Figure 21). MUXOUT needs to be set to the fastlock

switch to use the internal switch. For example, if the charge

pump current is increased by 16, the damping resistor, R1,

needs to be decreased by ¼ while in wide bandwidth mode.

ADF4153A

VCO

MUXOUT

R1A

Figure 21. ADF4153A with Fastlock

The value of R1A is then chosen so that the total parallel

resistance of R1 and R1A equals 1/4 of R1 alone. This gives

an overall 4× increase in loop bandwidth, while maintaining

stability in wide bandwidth mode.

When the PLL has locked to the new frequency, the charge

pump is again programmed to the lowest charge pump current

setting by setting the fastlock bit to 0. The internal switch opens

and the damping resistor reverts to its original value. This

narrows the loop bandwidth to its original cutoff frequency

to allow better attenuation of the spurs than the wide-loop

bandwidth.

SPUR MECHANISMS

The following section describes the three different spur mechan-

isms that arise with a fractional-N synthesizer and how to

minimize them in the ADF4153A.

Fractional Spurs

The fractional interpolator in the ADF4153A is a third-order

Σ-Δ modulator (SDM) with a modulus (MOD) that is program-

mable to any integer value from 2 to 4095. In low spur mode

(dither enabled), the minimum allowed value of MOD is 50.

The SDM is clocked at the PFD reference rate (FPFD) that allows

PLL output frequencies to be synthesized at a channel step

resolution of FPFD/MOD.

In lowest noise mode and low noise and spur mode (dither off),

the quantization noise from the Σ-Δ modulator appears as frac-

tional spurs. The interval between spurs is FPFD/L, where L is the

repeat length of the code sequence in the digital Σ-Δ modulator.

For the third-order modulator used in the ADF4153A, the repeat

length depends on the value of MOD, as shown in Table 6.

Table 6. Fractional Spurs with Dither Off

Condition (Dither Off)

Repeat

Length

Spur Interval

If MOD is divisible by 2, but not 3

2 × MOD

Channel step/2

If MOD is divisible by 3, but not 2

3 × MOD

Channel step/3

If MOD is divisible by 6

6 × MOD

Channel step/6

Otherwise

MOD

Channel step

In low spur mode (dither enabled), the repeat length is

extended to 221 cycles, regardless of the value of MOD, which

makes the quantization error spectrum look like broadband

noise. This can degrade the in-band phase noise at the PLL

output by as much as 10 dB. Therefore, for lowest noise, dither

off is a better choice, particularly when the final loop BW is low

enough to attenuate even the lowest frequency fractional spur.

Integer Boundary Spurs

Another mechanism for fractional spur creation is interactions

between the RF VCO frequency and the reference frequency.

When these frequencies are not integer related (which is the

point of a fractional-N synthesizer), spur sidebands appear on

the VCO output spectrum at an offset frequency that corresponds

to the beat note or difference frequency between an integer

multiple of the reference and the VCO frequency.

These spurs are attenuated by the loop filter and are more

noticeable on channels close to integer multiples of the

reference where the difference frequency can be inside the

loop bandwidth, therefore, the name integer boundary spurs.

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