ADF4153ABCPZ datasheet(3/24 Pages) AD

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Data Sheet

ADF4153A

Rev. A | Page 3 of 24

SPECIFICATIONS

AVDD = DVDD = SDVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted;

dBm referred to 50 Ω.

Table 1.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

RF INPUT CHARACTERISTICS (3 V)

See

Figure 12 for an input circuit

RF Input Frequency (RFIN)

0.5

GHz

−8 dBm minimum/0 dBm maximum

GHz

−10 dBm minimum/0 dBm maximum

For lower frequencies, ensure slew rate

(SR) > 400 V/µs

REFIN CHARACTERISTICS

See

Figure 11 for an input circuit

REFIN Input Frequency

250

MHz

For f < 10 MHz, use a dc-coupled,

CMOS-compatible square wave;

slew rate > 25 V/µs

REFIN Input Sensitivity

0.7

AVDD

V p-p

Biased at AVDD/21

REFIN Input Capacitance

REFIN Input Current

±100

µA

PHASE DETECTOR

Phase Detector Frequency

MHz

CHARGE PUMP

ICP Sink/Source

Programmable; see

Figure 19

High Value

With RSET = 4.7 kΩ

Low Value

312.5

µA

With RSET = 4.7 kΩ

Absolute Accuracy

2.5

With RSET = 4.7 kΩ

RSET Range

3.0

kΩ

ICP Three-State Leakage Current

Sink and source current

Sink and Source Matching

0.5 V ≤ VCP ≤ VP − 0.5 V

ICP vs. VCP

0.5 V ≤ VCP ≤ VP − 0.5 V

ICP vs. Temperature

VCP = VP/2

LOGIC INPUTS

VINH, Input High Voltage

1.4

VINL, Input Low Voltage

0.6

IINH/IINL, Input Current

±1

µA

CIN, Input Capacitance

LOGIC OUTPUTS

VOH, Output High Voltage

1.4

Open-drain 1 kΩ pull-up to 1.8 V

VOL, Output Low Voltage

0.4

IOL = 500 µA

POWER SUPPLIES

AVDD

2.7

3.3

DVDD, SDVDD

AVDD

5.5

IDD

Low Power Sleep Mode

µA

NOISE CHARACTERISTICS

Normalized Phase Noise Floor (PNSYNTH)2

−223

dBc/Hz

PLL loop BW = 500 kHz

Normalized 1/f Noise (PN1_f)3

−121

dBc/Hz

Measured at 10 kHz offset, normalized to 1 GHz

Phase Noise Performance4

@ VCO output

1750 MHz Output5

−107

dBc/Hz

@ 5 kHz offset, 25 MHz PFD frequency

AC coupling ensures AVDD/2 bias.

The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log(N) (where N is the N divider

value) and 10 log(FPFD). PNSYNTH = PNTOT − 10 log(FPFD) − 20 log(N).

The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, FRF,

and at an offset frequency, f, is given by PN = P1_f + 10 log(10 kHz/f) + 20 log(FRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL.

The phase noise is measured with the EV-ADF4153ASD1Z and the Rohde & Schwarz FSUP spectrum analyzer operating in phase noise mode.

fREFIN = 100 MHz; FPFD = 25 MHz; offset frequency = 5 kHz; RFOUT = 1750 MHz; N = 70; loop BW = 20 kHz; lowest noise mode.

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