ADF4153ABCPZ datasheet(8/24 Pages) AD

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ADF4153A

Data Sheet

Rev. A | Page 8 of 24

CIRCUIT DESCRIPTION

REFERENCE INPUT SECTION

The reference input stage is shown in Figure 11. SW1 and SW2

are normally closed switches. SW3 is normally open. When

power-down is initiated, SW3 is closed and SW1 and SW2 are

opened. This ensures that there is no loading of the REFIN pin

on power-down.

BUFFER

TO R COUNTER

REFIN

100k

Ω

SW2

SW3

SW1

POWER-DOWN

CONTROL

Figure 11. Reference Input Stage

RF INPUT STAGE

The RF input stage is shown in Figure 12. It is followed by a

2-stage limiting amplifier to generate the current-mode logic

(CML) clock levels needed for the prescaler.

BIAS

GENERATOR

1.6V

AGND

AVDD

2kΩ

RFINB

RFINA

Figure 12. RF Input Stage

RF INT DIVIDER

The RF INT CMOS counter allows a division ratio in the PLL

feedback counter. Division ratios from 31 to 511 are allowed.

INT, FRAC, MOD, AND R RELATIONSHIP

The INT, FRAC, and MOD values, in conjunction with the

R counter, make it possible to generate output frequencies that

are spaced by fractions of the phase frequency detector (PFD).

See the RF Synthesizer: A Worked Example section for more

information. The RF VCO frequency (RFOUT) equation is

RFOUT = FPFD × (INT + (FRAC/MOD))

(1)

where:

RFOUT is the output frequency of the external voltage controlled

oscillator (VCO).

INT is the preset divide ratio of the binary 9-bit counter (31

to 511).

FRAC is the numerator of the fractional division (0 to MOD − 1).

MOD is the preset fractional modulus (2 to 4095).

The PFD frequency is given by:

FPFD = REFIN × (1 + D)/R

(2)

where:

REFIN is the reference input frequency.

D is the REFIN doubler bit.

R is the preset divide ratio of the binary 4-bit programmable

reference counter (1 to 15).

RF R COUNTER

The 4-bit RF R counter allows the input reference frequency

(REFIN) to be divided down to produce the reference clock to

the PFD. Division ratios from 1 to 15 are allowed.

THIRD-ORDER

FRACTIONAL

INTERPOLATOR

FRAC

VALUE

MOD

REG

INT

REG

RF N DIVIDER

N = INT + FRAC/MOD

FROM RF

INPUT STAGE

TO PFD

N-COUNTER

Figure 13. RF N Divider

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