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Data Sheet

AD9510

Rev. C | Page 29 of 56

VCO/VCXO Feedback Divider—N (P, A, B)

The N divider is a combination of a prescaler, P (3 bits), and two

counters, A (6 bits) and B (13 bits). Although the PLL of the

AD9510 is similar to the ADF4106, the AD9510 has a redesigned

prescaler that allows lower values of N. The prescaler has both

a dual modulus (DM) and a fixed divide (FD) mode. The AD9510

prescaler modes are shown in Table 15.

Table 15. PLL Prescaler Modes

Mode

(FD = Fixed Divide,

DM = Dual Modulus)

Value in

Divide By

000

001

P = 2 DM

010

P/P + 1 = 2/3

P = 4 DM

011

P/P + 1 = 4/5

P = 8 DM

100

P/P + 1 = 8/9

P = 16 DM

101

P/P + 1 = 16/17

P = 32 DM

110

P/P + 1 = 32/33

111

When using the prescaler in FD mode, the A counter is not

used, and the B counter may need to be bypassed. The DM

prescaler modes set some upper limits on the frequency, which

can be applied to CLK2. See Table 16.

Table 16. Frequency Limits of Each Prescaler Mode

A and B Counters

The AD9510 B counter has a bypass mode (B = 1), which is not

available on the ADF4106. The B counter bypass mode is valid

only when using the prescaler in FD mode. The B counter is

bypassed by writing 1 to the B counter bypass bit (Register 0x0A[6]

= 1b). The valid range of the B counter is 3 to 8191. The default

after a reset is 0, which is invalid.

Note that the A counter is not used when the prescaler is in

FD mode.

Note also that the A/B counters have their own reset bit, which

is primarily intended for testing. The A and B counters can also

be reset using the shared reset bit of the R, A, and B counters

(Register 0x09[0]).

Determining Values for P, A, B, and R

When operating the AD9510 in a dual-modulus mode, the

input reference frequency, fREF, is related to the VCO output

frequency, fVCO.

fVCO = (fREF/R) × (PB + A) = fREF × N/R

When operating the prescaler in fixed divide mode, the A

counter is not used and the equation simplifies to

fVCO = (fREF/R) × (PB) = fREF × N/R

By using combinations of dual modulus and fixed divide modes,

the AD9510 can achieve values of N all the way down to N = 1.

Table 17 shows how a 10 MHz reference input can be locked to

any integer multiple of N. Note that the same value of N can be

derived in different ways, as illustrated by N = 12.

Table 17. P, A, B, R—Smallest Values for N

fREF

fVCO

Mode

Notes

P = 1, B = 1 (Bypassed)

P = 2, B = 1 (Bypassed)

P = 1, B = 3

P = 1, B = 4

P = 1, B = 5

P = 2, B = 3

P/P + 1 = 2/3, A = 0, B = 3

P/P + 1 = 2/3, A = 1, B = 3

P/P + 1 = 2/3, A = 2, B = 3

P/P + 1 = 2/3, A = 1, B = 4

100

P = 2, B = 5

100

P/P + 1 = 2/3, A = 0, B = 5

110

P/P + 1 = 2/3, A = 1, B = 5

120

P = 2, B = 6

120

P/P + 1 = 2/3, A = 0, B = 6

120

P/P + 1 = 4/5, A = 0, B = 3

130

P/P + 1 = 4/5, A = 1, B = 3

Mode (DM = Dual Modulus)

CLK2

P = 2 DM (2/3)

<600 MHz

P = 4 DM (4/5)

<1000 MHz

P = 8 DM (8/9)

<1600 MHz

P = 16 DM

<1600 MHz

P = 32 DM

<1600 MHz

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