AD9510 datasheet(21/56 Pages) AD

номер детали	AD9510

подробное описание детали	1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs

PDF	56 Pages

Scroll/Zoom	100%

производитель	AD [Analog Devices]

домашняя страница	http://www.analog.com

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21 / 56 page

Data Sheet

AD9510

Rev. C | Page 21 of 56

Figure 12. Phase Noise, LVPECL, DIV 1, FVCXO = 245.76 MHz,

fOUT = 245.76 MHz, fPFD = 1.2288 MHz, R = 25, N = 200

Figure 13. PLL Reference Spurs: VCO 1.5 GHz, fPFD = 1 MHz

Figure 14. Charge Pump Output Characteristics at VCPs = 3.3 V

Figure 15. Phase Noise, LVPECL, DIV 4, fVCXO = 245.76 MHz,

fOUT = 61.44 MHz, fPFD = 1.2288 MHz, R = 25, N = 200

Figure 16. Phase Noise (Referred to CP Output) vs. PFD Frequency (fPFD)

Figure 17. Charge Pump Output Characteristics at VCPs = 5.0 V

–10

–20

–30

–40

–50

–60

–70

–80

–90

CENTER 245.75MHz

30kHz/

SPAN 300kHz

100

–10

–20

–30

–40

–50

–60

–70

–80

–90

CENTER 1.5GHz

250kHz/

SPAN 2.5MHz

VOLTAGE ON CP PIN (V)

0.5

1.0

1.5

2.0

2.5

3.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

PUMP DOWN

PUMP UP

–10

–20

–30

–40

–50

–60

–70

–80

–90

CENTER 61.44MHz

30kHz/

SPAN 300kHz

PFD FREQUENCY (MHz)

0.1

100

–170

–165

–160

–155

–150

–145

–140

–135

VOLTAGE ON CP PIN (V)

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

PUMP DOWN

PUMP UP

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