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AD9510

Data Sheet

Rev. C | Page 32 of 56

FUNCTION PIN

The FUNCTION pin (16) has three functions that are selected

by the value in Register 0x58[6:5]. This pin is internally pulled

down by a 30 kΩ resistor. If this pin is left unconnected, the

part is in reset by default. To avoid this, connect this pin to VS

with a 1 kΩ resistor.

RESETB: Register 0x58[6:5] = 00b (Default)

In its default mode, the FUNCTION pin acts as RESETB, which

generates an asynchronous reset or hard reset when pulled low.

The resulting reset writes the default values into the serial control

port buffer registers as well as loading them into the chip control

registers. When the RESETB signal goes high again, a synchro-

nous sync is issued (see the SYNCB: Register 0x58[6:5] = 01b

section) and the AD9510 resumes operation according to the

default values of the registers.

SYNCB: Register 0x58[6:5] = 01b

Using the FUNCTION pin causes a synchronization or

alignment of phase among the various clock outputs. The

synchronization applies only to clock outputs that

•

Are not powered down

•

The divider is not masked (no sync = 0b)

•

Are not bypassed (bypass = 0b)

SYNCB is level and rising edge sensitive. When SYNCB is low,

the set of affected outputs are held in a predetermined state,

defined by the start high bit of each divider. On a rising edge,

the dividers begin after a predefined number of fast clock cycles

(fast clock is the selected clock input, CLK1 or CLK2) as

determined by the values in the phase offset bits of the divider.

The SYNCB application of the FUNCTION pin is always active,

regardless of whether the pin is also assigned to perform reset

or power-down. When the SYNCB function is selected, the

FUNCTION pin does not act as either RESETB or PDB.

PDB: Register 0x58[6:5] = 11b

The FUNCTION pin can also be programmed to work as an

asynchronous full power-down, PDB. Even in this full power-

down mode, there is still some residual VS current because

some on-chip references continue to operate. In PDB mode,

the FUNCTION pin is active low. The chip remains in a power-

down state until PDB is returned to logic high. The chip returns

to the settings programmed prior to the power-down.

See the Chip Power-Down or Sleep Mode—PDB section for more

details on what occurs during a PDB initiated power-down.

DISTRIBUTION SECTION

As previously mentioned, the AD9510 is partitioned into two

operational sections: PLL and distribution. The PLL Section is

discussed previously in this data sheet. If desired, the distribution

section can be used separately from the PLL section.

CLK1 AND CLK2 CLOCK INPUTS

Either CLK1 or CLK2 can be selected as the input to the distri-

bution section. The CLK1 input can be connected to drive the

distribution section only. CLK1 is selected as the source for the

distribution section by setting Register 0x45[0] = 1. This is the

power-up default state.

CLK1 and CLK2 work for inputs up to 1600 MHz. A higher input

slew rate improves the jitter performance. The input level must

be between approximately 150 mV p-p to no more than 2 V p-p.

Anything greater may result in turning on the protection diodes

on the input pins, which may degrade the jitter performance.

See Figure 35 for the CLK1 and CLK2 equivalent input circuit.

These inputs are fully differential and self-biased. The signal

must be ac-coupled using capacitors. If a single-ended input

must be used, this can be accommodated by ac-coupling to one

side of the differential input only. Bypass the other side of the

input to a quiet ac ground by a capacitor.

Power down the unselected clock input (CLK1 or CLK2) to

eliminate any possibility of unwanted crosstalk between the

selected clock input and the unselected clock input.

DIVIDERS

Each of the eight clock outputs of the AD9510 has its own

divider. The divider can be bypassed to obtain an output at the

same frequency as the input (1×). When a divider is bypassed,

it is powered down to save power.

All integer divide ratios from 1 to 32 can be selected. A divide

ratio of 1 is selected by bypassing the divider.

Each divider can be configured for divide ratio, phase, and duty

cycle. The phase and duty cycle values that can be selected

depend on the divide ratio that is chosen.

Setting the Divide Ratio

The divide ratio is determined by the values written via the serial

control port (SCP) to the registers that control each individual

output, OUT0 to OUT7. These are the even numbered registers

beginning at Register 0x48 and going through Register 0x56.

Each of these registers is divided into bits that control the

number of clock cycles that the divider output stays high

(HIGH_CYCLES[3:0]) and the number of clock cycles that the

divider output stays low (LOW_CYCLES[7:4]). Each value is 4

bits and has the range of 0 to 15.

The divide ratio is set by

Divide Ratio = (HIGH_CYCLES + 1) + (LOW_CYCLES + 1)

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