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Data Sheet

AD9510

Rev. C | Page 39 of 56

SINGLE-CHIP SYNCHRONIZATION

SYNCB—Hardware SYNC

The AD9510 clocks can be synchronized to each other at any

time. The outputs of the clocks are forced into a known state

with respect to each other and then allowed to continue clocking

from that state in synchronicity. Before a synchronization is

done, the FUNCTION Pin must be set to act as the SYNCB:

Synchronization is done by forcing the FUNCTION pin low,

creating a SYNCB signal and then releasing it.

See the SYNCB: Register 0x58[6:5] = 01b section for a more

detailed description of what happens when the SYNCB:

Soft SYNC—Register 0x58[2]

A soft SYNC can be issued by means of a bit in Registers 0x58[2].

This soft SYNC works the same as the SYNCB, except that the

polarity is reversed. A 1 written to this bit forces the clock outputs

into a known state with respect to each other. When a 0 is

subsequently written to this bit, the clock outputs continue

clocking from that state in synchronicity.

MULTICHIP SYNCHRONIZATION

The AD9510 provides a means of synchronizing two or more

AD9510s. This is not an active synchronization; it requires user

monitoring and action. The arrangement of two AD9510s to be

synchronized is shown in Figure 43.

Synchronization of two or more AD9510s requires a fast clock

and a slow clock. The fast clock can be up to 1 GHz and can be

the clock driving the master AD9510 CLK1 input or one of the

outputs of the master. The fast clock acts as the input to the

distribution section of the slave AD9510 and is connected to its

CLK1 input. The PLL can be used on the master, but the slave

PLL is not used.

The slow clock is the clock that is synchronized across the two

chips. This clock must be no faster than one-fourth of the fast

clock, and no greater than 250 MHz. The slow clock is taken

from one of the outputs of the master AD9510 and acts as the

REFIN (or CLK2) input to the slave AD9510. One of the outputs

of the slave must provide this same frequency back to the CLK2

(or REFIN) input of the slave.

Multichip synchronization is enabled by writing

the STATUS pin becomes the output for the SYNC signal. A low

signal indicates an in-sync condition, and a high indicates an

out-of-sync condition.

the maximum separation of the slow clock edges that are con-

sidered synchronized. When Register 0x58[1] = 0 (default), the

slow clock edges must be coincident within 1 to 1.5 high speed

clock cycles. If the coincidence of the slow clock edges is closer

than this amount, the SYNC flag stays low. If the coincidence of

the slow clock edges is greater than this amount, the SYNC flag

is set high. When Register 0x58[1] = 1b, the amount of coincidence

required is 0.5 fast clock cycles to 1 fast clock cycles.

Whenever the SYNC flag is set high, indicating an out-of-sync

condition, a SYNCB signal applied simultaneously at the

FUNCTION pins of both AD9510s brings the slow clocks into

synchronization.

Figure 43. Multichip Synchronization

AD9510

MASTER

FAST CLOCK

<1GHz

SLOW CLOCK

<250MHz

AD9510

SLAVE

FAST CLOCK

<1GHz

SLOW

CLOCK

<250MHz

SYNC

DETECT

CLK2

REFIN

OUTY

OUTM

OUTN

FSYNC

STATUS

(SYNC)

FUNCTION

(SYNCB)

FUNCTION

(SYNCB)

SYNCB

CLK1

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