REVISION B 6/11/15

8516 DATA SHEET

5

LOW SKEW, 1-TO-16

DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP

A

A

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

V

OD

Differential Output Voltage

250

400

600

mV

OD

V

50

mV

V

OS

Offset Voltage

1.125

1.4

1.6

V

OS

V

50

mV

I

OZ

High Impedance Leakage Current

-10

+10

µA

I

OFF

Power Off Leakage

-1

+1

µA

I

OSD

Differential Output Short Circuit Current

-5.5

mA

I

Output Short Circuit Current

-12

mA

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

f

MAX

Output Frequency

700

MHz

t

PD

Propagation Delay; NOTE 1

1.6

2.0

2.4

ns

tsk(o)

Output Skew; NOTE 2, 4

90

ps

tsk(pp)

Part-to-Part Skew; NOTE 3, 4

500

ps

tjit

Buffer Additive Phase Jitter, RMS;

refer to Additive Phase Jitter Section

Integration Range:

12kHz - 20MHz

148

fs

t

Output Rise/Fall Time

20% to 80%

100

550

ps

odc

Output Duty Cycle

45

50

55

%

t

Output Enable Time; NOTE 5

5

ns

t

Output Disable Time; NOTE 5

5

ns

NOTE 1: Measured from the differential input crossing point to the differential output crossing point.

NOTE 2: Defined as skew between outputs at the same supply voltages and with equal load conditions.

Measured at the output differential cross points.

NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages

and with equal load conditions. Using the same type of inputs on each device, the outputs are measured

at the differential cross points.

NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.

NOTE 5: These parameters are guaranteed by characterization. Not tested in production.