REVISION B 6/11/15

8516 DATA SHEET

3

LOW SKEW, 1-TO-16

DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP

Inputs

Outputs

OE1

OE2

Q0:Q7

nQ0:nQ7

Q8:Q15

nQ8:nQ15

0

0

Hi Z

Hi Z

Hi Z

Hi Z

1

0

ACTIVE

ACTIVE

Hi Z

Hi Z

0

1

Hi Z

Hi Z

ACTIVE

ACTIVE

1

1

ACTIVE

ACTIVE

ACTIVE

ACTIVE

In the active mode, the state of the outputs are a function of the CLK and nCLK inputs as described in Table 3B.

Inputs

Outputs

Input to Output Mode

Polarity

CLK

nCLK

Q0:Q15

nQ0:nQ15

0

1

LOW

HIGH

Differential to Differential

Non Inverting

1

0

HIGH

LOW

Differential to Differential

Non Inverting

0

Biased; NOTE 1

LOW

HIGH

Single Ended to Differential

Non Inverting

1

Biased; NOTE 1

HIGH

LOW

Single Ended to Differential

Non Inverting

Biased; NOTE 1

0

HIGH

LOW

Single Ended to Differential

Inverting

Biased; NOTE 1

1

LOW

HIGH

Single Ended to Differential

Inverting

NOTE 1: Please refer to the Application Information section, “Wiring the Differential Input to Accept Single Ended Levels”.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

C

IN

Input Capacitance

4

pF

R

PULLUP

Input Pullup Resistor

51

k

Ω

R

PULLDOWN

Input Pulldown Resistor

51

k

Ω

C

PD

Power Dissipation Capacitance

(per output)

4pF